Digital Electronic System - Lab Report Example

DIGITAL ELECTRONIC SYSTEM By Task: A report on the lab designand implementation of theserialtransmitterusing multiplexers Abstract The lab report is based on the design and simulation of Asynchronous Serial Data Transmission using the multisim software. The report covers the various design methods including Parallel to serial conversion; use of higher-level logic constructs, forthiscase, the multiplexers. The report also includes the formal design methodologies that include the use of truth tables, Karnaugh maps, use of Boolean algebra andthe de Morgan’s Laws. Introduction A Universal Asynchronous Receiver Transmitter (UART) is a programchipused to manage a computer’s interface to its peripheral serial devices. UART receives parallel bytes of data from the computer and transmits the individual bits in sequential form. At thereceivingend, a corresponding UART receives and re-assembles thebits in complete bytes by addingstartbits, stopbitandparitybit in their transmission (Breuer & Friedman, 2011). For a UART to functionproperly, it must be in full duplex mode. Data thus is transmitted in two directionssimultaneously. Asynchronous serial data transmission protocols involve sending data serially. Serialdatatransfer is a form of transmission where bits of characters are sent one at a time along a communicationpath that must be at a knowntransmissionratecalledthe baud rate. However, there are two types of serial data transmission. These are: Synchronous serialcommunicationand Asynchronous serialtransmission. Synchronousserialcommunication is a serialcommunicationsprotocolwheredatais sent in a continuousstream at a constantrate. For Synchronous Communication, clocks in thetransmitting andreceivingdevices must be synchronized, running at thesameratesothatthereceiver can samplethesignal at thesametimeandintervalsused by transmitterandnostartorstopbitsare required. In synchronousserialcommunication, data is sent as frames of largedatablocks. Asynchronous serial transmission does not require sending or receiving idle characters. However, thebeginningandend of each byte of data must be identified by startsandstopbits. Thestartbitshowswhenthe byte containingdata is to beginandthestopbittransferwhenitends. Therequirement cause asynchronous communications to be slightlyslower than synchronous. Theadvantage is thatthe processor does not have to deal with theadditionalidlecharacter. It is simple to implement an asynchronous serialtransmitterusing a 10-bit shiftregisterand a littleextrahardware. Aready to be transmittedcharacter is loadedparallel into theshiftregistertogether with startandstopbits after which data is thenshifted out at the baud rate until theshiftregister has a value of zero. An asynchronous receiver is harder to implement an asynchronous receiver since thetransmitterandreceiver are asynchronous to eachother, andnewcharacter may startarriving at anytime. Somemethod is needed to synchronize thereceiver with the incoming data (March & Smith, 2014). Themostcommonmethod of synchronizing thereceiver with thereceiveddata is to clockthereceivercircuit at a factor of the baud rateand to samplethe incoming data to determinethefallingedge of thestopbit. Asynchronous serialcommunication is advantageous since it has lesstransmissionline, highreliability, andlongtransmissiondistance, therefore, is widelyused in dataexchange between computerand peripherals. This Asynchronous serial communication is usually implemented by UART transmission protocol. Basictheory A UART is morepreferredstandardcommunicationsfor its low-cost, low-speed serial over a mere 2- wire interface. Asynchronous communications is different from synchronouscommunications in that synchronization between transmitterandreceiver are encoded into thetransmittedsignal, instead of using a separate wire to transferthetransmitterclock to thereceiver. Usually, asynchronous communication modes facilitate lower data rates compared with synchronous modes. This isbecause asynchronous communications may imposestrongerrequirements on the transceivers andthetransmissionlines between receiverandtransmitter. Lowcostandlowpower transceivers usuallydo not haveadvancedclockrecoverymechanisms, butjust depend on thecombination of oversampling andthatthereceiverandtransmitterclockfrequencies are sufficientlyclose (March & Smith, 2014). Design methodology Agooddesign must be in its simplestformmeaningthatvariousoperations must be carried out in theinitialexpression(s) so as to come up with thesimplestfinalexpression. Thefirstinterpretation of a designproblem is usually in theform of a Boolean equation. A Boolean equation must, however, be reduced to its simplestfinalexpression before its implementation. A simplified expression ensures the use of a smaller number of gates, with eachgate (other than Inverter) havinglessnumber of inputs, thus, reducingthecost of the implementation. There are two methodsfor simplification of Boolean functions, these methods are: The algebraic method by using Identities The graphical method using Karnaugh Map method commonly referred to ask maps. A Karnaugh map is a pictorial methodused to minimize Boolean expressions without havingnecessary to use Boolean algebra theoremsandequationmanipulations. A K-map thus can be termed as a particularversion of a truthtable. The K-map method is easyandstraightforward since itdoes not involvelengthyandtediouscalculations. A K-map for a function of individual n variables has 2 n cells. In everyrowandcolumn, two adjacentcells should containdifferentvalue of only one of thelogic variables; hence a k map can be 2 variables, 3 variables or 4 variables depending on theinitialexpression of the Boolean function. The algebraic method of using Identities is however not commonlyused due to its intricateformalitiesinvolvedcompared to the k mapmethod. Anotherformalaspect of designing a digital system is the Parallel to serialconversion. Parallel to serialconversionmostlyuses a shiftregister. A serial-in-parallel-out shiftregister is similar to the serial-in-serial-out shiftregister in thatitmoves data into internalstorageelements. It also shifts data out at the serial-out, data-out, and pin. A serial-in/parallel-out shift register converts data from a serialformat to parallelformat. Theactualapplication of the serial-in-parallel-out shiftregister is to change data from serialformat on a singlewire to parallelmultiplewires. Serial-in-parallel-out shift register are used as long as it has nomore than 8-bits. Serial-in-serial-out shift registers come in bigger than 8-bit lengths of 18 to 64-bits. Offering a 64-bit serial-in-parallel-out shift register requiring many output pins are not practical since it would result in abnormal waveforms as, could be observed on a Cathode Ray Oscilloscope. According to March & Smith (2014), designing process requires another essential aspect and process that involve the use of truth tables. Atruthtable is a mathematical tabular methodused in thelogicanalysis in connection with Boolean algebra, Boolean functions, and propositional calculus. Atruthtable is used to computethefunctionalvalues of logicalexpressionseach on their substantive arguments. A truth table indicates how the output of a logic circuit corresponds to numerous combinations of its inputs, wherelogic 1 representstrue/high/on andlogic 0 representsfalse/low/off. Allpossiblepermutations of theinputsare listed on theleft, andthecorrespondingoutput of thecircuitlisted on theright. Consequently, thedesiredoutput can be achieved by a combination of logicgates. Atruthtable can have two inputs that can be stretched to a number of inputs. Theinputcolumns are constructedfollowingtheorder of binary. Truth tables help understand the behaviors of logic gates since they show how the input(s) of a logic gate relate to its output(s). Truthtables can alsohelpunderstandthebehaviors of combinations of logicgateslinkedtogether as theyare drawn in thesameway as before, butthistimeaddingmorecolumns in between theinputandoutputcolumns. Each of the new columns shows the outputs of stages in the logic circuit. Structure of a UART A UART usually contains four essential components that enable its functionality. The four components are: 1. Aclockgenerator to allow sampling in the middle of a bit period 2. Input and output shift registers 3. Transmit and receive control 4. Read and/or write control logic However, to improve the functionality of the UART depending on theconditions, someoptionalcomponents may be added. Theyincludeelements like transmitand/orreceiverbuffers, parallel data busbufferand First-in-first-out buffermemory (Sanchez, 2010). In the lab, the design and simulation of the UART involved the use of a multiplexer. A procedure was followed so as to come up with thedesiredandaimeddesign of the UART. Lab procedure 1. Data was loaded into a parallel in, parallel-out shiftregister. 2. A 10 to 1 multiplexer, whereby a 16 to 1 could alsobe used with thelast 6 bitsbeingunused, hadinput 0 connected to logic 0, bits 1 to 8 connected to theshiftregisterandbit 9 connected to logic 1.Theremaining (unused) bitswerealsoconnected to logic 1.In the multiplexer, logic 1 acted as a startbit. 3. Multiplexer outputwasinvertedand level shifted to fitthe RS232 format trigger pulse resets a counter to zero in order to transmit a character which thengeneratedtheoutputsequence 0000, 0001,0010,0011,0100, 0101, 0110, 0111, 1000,1001(0-9).At 1001, thecounterstoppedcountingandremained in theposition until reset to zero. 4. Thecounter trigger pulsewassynchronous with theprimary timing clocksothatthetransmitterandthereceiver could be synchronous. 5. Theoutput of thecounterfedtheselectlines of the multiplexer. AD- flip flop wasused to dothe retiming of the multiplexer to eliminate the glitches at bit transitions. During Multisim Simulation, the available TTL family was used but during hardware implementation, thedesignwasattached to thoseprovided by the Logic Boards. Procedure 3(count to 9 andstop) wasconsideredthefundamentalprinciple of operation since itgavethe multiplexer’s selectlinesinput. Before implementing, the counters were first tested. The multiplexer was also tested separately with its Select inputs coming initially from bit patterns stored in the Word Generator (Sanchez, 2010). The Logic Analyzer monitored the serial output and confirmed that the bit sequence was correct. Resultsandobservations After simulating the design using Multisim 12.0 (Simulation program), a design of the format below was obtained. Subsequently, after successful simulation of the model using the Multisim simulation software, the design was now ready to be worked on in thelaboratory by creatingtheactualcomponents on the two boardsprovided. Acompletedesign of the Asynchronous Serial Data Transmission was as seen below (Venkatesh, et al., 2013). After implementingthedesign on theboards, an Oscilloscope wasused to measuretheoutputparameters of thedesignusingbothchannels of the oscilloscope. For uniformity of the results and improved accuracy, both channel one probe and channel two probe were set to be *10. Square waves were observed on both channels. However, the waves were not perfect square waves as expected but were noted to have some distortions as seen below. Working principle of the design the design of the serial transmission comprised the use of multiplexers and DE multiplexers and a 74193 counterchip. In the design procedure, the counter was used to count the binary bit from 0 (binary bit 0000) to 9(binary bit 1001). The counter is clocked so that after counting up to 9(1001), the count returns to 0(0000). The 74151 8*1 multiplexer was used in combinational with the 74115 chip. The DE multiplexer primarily a back with one inputand two outputs that wereselected by N selectlineswasused in the combinational design. A 1 to 8 DE multiplexer was constructed from 74115 dual 1 to 4 DE multiplexer. This isessentially a DE multiplexer which has one inverting input (Sanchez, 2010). Time multiplexing was used to reduce the amount of power required to transmit the bits from the transmission end to the receiving end. Itwasalsousedforindependent data streams must be sent over a single line or channel. Source of errorexplanations Thedistortiondetected on the oscilloscope was as a result of interference of thesignalcaused by lack of properand/orenough filtration of thesignal. The possible source of interference was influenced by the output of the filter. Filters often pose a significant unwanted impulse possibly causing distortion. Thisdistortion should be carefully quantified by use of correct filters (capacitors and resistors forthiscase) Asynchronous serial data transmissionsignal timing is not required since signals are sent in an agreedpattern of bits, andifbothends (receivingandtransmittingend) are decided on thepatternsothatcommunication can takeplace.Bits are groupedtogether consisting of both data andcontrolbits. For unsynchronized signal, thereceiver will not be able to distinguishwhenthenextgroup of bits will arrive (Venkatesh, et al., 2013). This isovercome by precedingthe data by a startbit, usuallybinary 0, the byte is thensent, and a stopbitorbitsare added to theend. Each byte to be sent now incorporates extra control data. In asynchronous transmission, every bit remains timed in the usual way. At bit level, thecommunication is stillsynchronous (timed). However, the asynchronous transmission is applied at the byte level, once thereceiverdetects a chunk of incoming data timing (synchronization) takes place for the piece of data. Conclusion From the lab activity, it was noted that Serial communication is used for all long-haul communication and most widespread in the Computer and Telecommunication industrywherethecost of cableand synchronization difficultiesmakeparallelcommunicationimpractical. Serialbuses are morecommoneven at shorterdistances due to theimprovedsignalintegrity, andtransmissionspeeds in latestserial technologies havebegun to outweighothertransmissionmethodsincludingtheparallelbuss advantage of simplicity. Serial buses have also reduced the cost that was initially induced by integrated circuits that have more pins. To cutthepins, many Integrated Circuits use a serialbus to transfer data especiallywhenspeed is not a crucialaspect in transmission. As from theactivity, itwasclearthattheserialtransmissionusually consists of 9 pins that connectthedata in a series, hencethenameserialport. Using multisim simulation software to design a serialcommunicationgave a clearindication of how multiplexers can be used alongside counters to transmit data hence from theserialdatatransmission. Further implementing the design on the board also gave an apparent aspect of the physical properties and the structure of the asynchronous serialdatatransmissionlayout. References Breuer, M. A., & Friedman, A. D. (2011).Diagnosis and reliable design of digital systems. Digital System Design Series, London: Pitman, 1977, 1. Kleijnen, J. P., Sanchez, S. M., Lucas, T. W., &Cioppa, T. M. (2012). State-of-the-art review: a user’s guide to thebravenewworld of designing simulation experiments. INFORMS Journal on Computing, 17(3), 263-289. March, S. T., & Smith, G. F. (2014).Designandnaturalscienceresearch on information technology. Decisionsupportsystems, 15(4), 251-266. Sanchez, S. M. (2010). Worksmarter, not harder: guidelines fordesigning simulation experiments. In Proceedings of the 37th conference on winter simulation (pp. 69-82).Winter Simulation Conference. Soderstrand, M. A., Jenkins, W. K., Jullien, G. A., & Taylor, F. J. (2013).Residuenumbersystemarithmetic: modernapplications in digital signal processing. IEEE Press. Venkatesh, V., Morris, M. G., Davis, G. B., & Davis, F. D. (2013). User acceptance of information technology: Toward a unifiedview. MIS Quarterly, 425-478. Read More