Testing Analog and Mixed Signal Circuits With Built In Hardware - Research Paper Example

System-on-chips (SOCs) with built-in hardware and analog mixed-signal embedded-core-based are intended to be tested with the help of this paper. In this article the method used for testing the components of analog mixed-signal circuit is oscillation-based built-in self-test (OBIST). Moreover, in association with the components of analog-circuit the OBIST composition is used for the on - chip generation of oscillatory responses. In the mixed signal SOCs environment, OBIST method is suitable for testing analog-circuit since, it does not involve any complex response analyzers and stimulus generators. HSPICE explains the wide-ranging simulation on sample analog and mixed-signal circuits and other added circuits. Chapter I : Introduction System designers and test engineers are motivated in modern years to divert their research towards the escalating applications of analog and mixed-signals embedded-core-based system-on-chips (SOCs), in order to expand their research for the significant testing strategies of integrated circuits and systems. Before beginning definite manufacturing of high-volume products, the testing, designing, assessment of the prototypes are important. Furthermore, the comprehensive inspection of the manufactured products must be done in order to ensure the availability of high quality and defect free product. Eventually the cost of the product can be minimized by providing the required information during the manufacturing process. The fabrication procedure of the integrated-circuit (IC) comprises doping steps, etching, printing and photolithography. The reason for the collapse of an individual integrated-circuit (IC) is the imperfect steps related to the fabrication process. Above all, the mixed-signal ICs are more responsive towards steps imperfections thus, resulting in low performance of circuits. However, these imperfections are insignificant in the digital - circuit domain but as compared to the mixed-signal circuits, imperfections among the traces in structure of small capacitance can cause a significant change in the circuit performance. For this reason, the sensitivity behavior of the circuit also improved due to the reduction of the circuit geometry. Hence, before shipping it to the customers every single IC is being thoroughly checked. This priority testing of ICs enhances the final quality of the product without affecting its brilliance. In addition, this quality check also ensures the excellence of the product and its design, during the key phase of the product development once put into practice. The detailed and long tests are being performed during the process of implementation of the ICs due to the small imperfection of the high sensitivity of mixed-signal circuits resulting in the high testing cost. Now researchers are looking forward to merge the testing process of both analog and the digital-circuit via analog signals to divert digital circuits or by utilizing digital signals for example, serial bit stream in order to divert the analog signals. The analog-test methods are not fully developed, therefore restricted access is suffered by mixed-signal specially; the shrinking dimensions with the high integration densities in the development of semi-conductor technology. On the other hand, the test systems related to the digital devices are well maintained and developed. However, the benefits are taken from the advancement and knowledge of digital-test by the analog and mixed-signal test, because they are far away from the latest development regarding testing procedures. Another reason for the failure of the analog testing system is the deficiency of the implementation of a testing procedure for example, Standard Fault Model, however, approximately all the digital test methods rely on stuck-fault model thus, with the help of their fault reporting, the test generation algorithms are estimated. This model is simply accepted for the functional test as compared to the performance test, it is not accepted. The sources of complexity during the testing procedures of analog circuit and digital circuits are different for instance, in analog and mixed-signal circuit the performance of circuit signals are more important as compared to the size of a circuit. On contrary, in digital circuits the size and the complication of a circuit is a major issue regarding testing procedure. There is a doubt in the quantification of the product, while testing analog and mixed-signal-circuits due to the thin separation line among fault-free and faulty circuits. The definition of coverage of fault in analog and mixed-signal-circuits is ‘The percentage ratio of the number of faults detected to the total number of possible circuit faults.’ The development in the field of mixed-signal circuits and electronic-packaging is increasing immensely neglecting the reduction in the size of ICs. The analog circuits are put together so closely with the digital matching parts resulting, complexity in testing procedure. Moreover, an added requirement occurs on mixed-signal-circuits, while the progression of interfacing several systems. As the mixed-signal ICs are growing rapidly, the demand for the test conduction on mixed-signal is also increasing. Furthermore, mixed-signal test procedures require massive development because the methods related to the analog and digital-tests have become a part of discussion in industries and educational institutes. The testing procedure of mixed-signal circuits is filled with complications and challenges therefore; in mixed-signal device, the semiconductor industry is looking forward to discover an additional ways of testing analog portions in order to reduce the cost. Approximately only 10% of the cost is utilized by the analog parts and chip-areas while, the 85% of the cost is occupied in testing procedures of analog functions. Thus it is necessary to cut the cost related to the analog testing process. Basically test is conducted to verify the specifications of circuit-design that is required. The restricted test pins and the complication in SOCs limit the access of mixed-signal parts of SOCs from the outside. However, the design-for-test (DFT) strategies enhances the convenience to the node either to manage or to examine a circuit. Therefore, development of test program, classification of designs, increase in the quality of products, and reduction in test costs can be achieved by the implementation of the DFT method. Test buses and scan chains are consumed In order to improve the controllability and testability of interior nodes. The long wires are made for the transmissions of the outer signals as a result these signals are calculated and developed; on the other hand, analog signals are debased throughout transmission. Due to this decrease in production arises because of the inaccurate test results. The Built-in-self-test method (BIST) is a feasible solution for the above mention issue. The term BIST is a combination of two ideas i.e. built-in-test (BIT) and ST. The built-in-self-test method (BIST) manages problems related to the test-analog, mixed-signals and digital systems. By implementing BIST test functions, test production and test confirmation can be attained. Furthermore, testing can be finished with the help of built-in hardware, of different parts of chips in the corresponding method thus reducing time and other requirements of external testing equipment. The major issue is still the huge testing cost related to the new products that are manufactured however, by performing BIST on new products the cost of maintaining and manufacturing can be lowered via advanced diagnoses. Fig 1 shows how to utilize the test-pattern generator (TPG----stimulus source) in a usual BIST atmosphere. The function of TPG is to drive its outputs towards circuit under test (CUT) and to feed the output from CUT into a test data analyzer. Moreover, if the test progression comes out differently as compared to the fault-free circuit an error is identified. The fault-free reactions from the CUT and the comparator are stocked up in a response compaction unit (RCU) that is included in the test data analysis. The decline in quality test for analog section is based on following points Deficiency of typical fault-model for mechanism of mixed-signal or analog circuits. Analog requirements expansion. Conducting imperfect set of tests. In this article new and advanced test methods are examined for mixed-signal embedded-core-based SOC background based on oscillation-based BIST (OBIST) structural design. Moreover, the principle discussed on the OBIST technique is to transform a specified circuit in order to make it testable. For this purpose a characterized fault model and test algorithms also uncover in this article. Results related to the set of choosing analog and mixed-signal circuits are specified to exhibit the effectiveness, possibility, and significance of the proposed implementation. Chapter II: Mixed-signal ICs and OBIST The analog and mixed-signal designers implemented extraordinary amount of functionality of a system on to a solo chip, with the help of process technology. The application-specific IC (ASIC) world and the custom IC world, both are the types of SOCs. This type of design is incorporated with the analog devices and it is also digitally integrated by embedded software. By spending reasonable time and cost over the analog and mixed-signal blocks the integration of the systems can be achieved. The analog and mixed-signal design that is the final kind of design comprises complex signal routes and better performance by in cooperation with analog and digital components. In fig 2 illustrates a model of the main components of a mixed-signal SOC here, the core components inclines to become Digital-to-Analog converter (DAC), random-access memory (RAM), phase-locked loop (PLL), logic and other components. The design stream of analog and mixed-signal SOCs is demonstrated in fig 3. Many strategies related to the fault-base testing of analog and mixed-signal circuits are projected in numerous literatures. The perception of OBIST needs to be mentioned especially because for testing circuits, it does not involve any modification of the CUT. The oscillation-based test technique (OBT) can be useful for both online and offline circuits testing. Furthermore, the expensive way of testing generators or specifications are not required in this method of testing. However, certain aspects for example viz., portioning of systems, type of response, essential measurements, fault reporting and others must be measured before applying OBT in any system. In this procedure the difficult analog circuits are divided into useful building blocks for instance, PLLs, comparators, filters, operational amplifiers (Op Amp) and many more. By adding accurate circuitry, the building blocks are transformed into oscillators, resulting in a continuous oscillation. The parameters regarding the oscillation are estimated subsequently. Moreover, the analog testing can be identical because the oscillation parameters are self-regulating of the CUT-type. However, under fault-free circumstances with the help of oscillation parameters, the faulty circuit is departed from the oscillation parameters. The fig4 describes the policy towards the OBT. For instance, the oscillation parameters include frequency, amplitude, distortion, or DC level of the output signal. In this method some faults can be discovered that are not related to the frequency provided that, this method offers full fault coverage by allowing for the oscillation frequency. In the above mentioned case, other methods for testing can be taken into consideration for example, by adding oscillation frequency and output voltage; fault coverage can be enhanced by monitoring the supply current. With the help of the output test signals numerous techniques are anticipated to remove the oscillation parameters. In order to estimate the output signals that are coming off the OBT-technique application, a simple method is suggested. According to this method output of the CUT is connected to a delta-sigma (??) therefore, providing a train of pulses including all the useful information about the output of the CUT. An automatic test equipment (ATE) or on-chip digital processor is used to process the pulses in order to pull out the oscillation parameters. The techniques related to the implementation for the OBIST might differ depending on the tradeoffs among the test time and the area overhead. The execution of BIST on biquad filters is described by three approaches therefore; switchable Op Amp (sw-Op Amp) is used in this article. In the foremost approach when each phase is having a comparator, each and every block of the building are transformed into oscillators concurrently. As a result, the test time is reduced with the help of an additional hardware. The second approach defines that, By means of sw-Op Amp and an analog multiplexer, each block is consecutively converted into an oscillator while one comparator is in use. In the third approach only one block is converted at a time into an oscillator, with the help of sw-Op Amp to pass up the signals from their inputs. Furthermore, the assessment is done consecutively. By using the second and third approach mentioned above, the continuity of the blocks can be tested yet more time is required for testing. In various circuits such as viz., filters, analog-to-digital converters etc. the OBT technique is functional. Moreover, this method is also applied on dual-tone multi frequency detector, digitally programmable switched-current biquad, and switched-capacitor circuits and analog Microcell. Similarly in smart sensor devices and complementary-symmetry metal-oxide semiconductors (CMOS) micro electro mechanical systems (MEMS) this method is also applied. It is time consuming to determine an accurate frequency of oscillation. A time-division-multiplexed (TDM) is anticipated to use as test architecture. When the CUT is transformed into an oscillator than the oscillation waveform is evaluated by the two suggested voltages, hence, the results are accumulating in counters by time-division-multiplexer (TDM). The method related to the OBIST in order to test the analog and mixed-signal circuits are described below Building an Oscillator Numerous methods have been projected for constructing an oscillator such as a method for transforming active RC filter into an oscillator that is published by Zarnik and his colleagues working on the research. Likewise, there is another method for constructing a design of a sinusoidal oscillator that is derived from a transfer function. The transfer function links with the output interface of the terminal i.e. the filter to the input interface. The common requirements associated with oscillation are a feedback signal that originates from the output to the input of adequate amplitude and proper phase. Likewise, there are few oscillators that utilize RC elements for the phasing process. Moreover, others functions on presentation of negative resistance principles considered as a feedback element. The equations associated with the design of an oscillator are identified by determining the denominator for the equation of the transfer i.e. T(s) of the circuit. The time domain behavior along with the stability of the system is determined by the poles of the denominator of a characteristic equation T(s). Likewise, the location of the oscillator is on the boundaries of a stable and unstable system, as it is created when the imaginary axis incorporates pairs of poles. Moreover, the magnitude associated with the phase equation of an oscillator also needs to be examined. In case of a magnitude for a loop gain is high or exceeding the value 1 and at the same time the phase value is 0, oscillation amplitude will escalate exponentially. The only factor that will seize the growth is the supply voltage. Moreover, if the scale of the loop gain is showing a value less than 1, the oscillation amplitude will be reduced to 0. Fault Model The fault model defines the two types of faults i.e. hard faults and soft faults that can take place while testing an analog circuit. The hard faults also identified as catastrophic faults are those that can allow any analog circuit to perform disastrously different from standard conditions. Furthermore, stuck-fault model and hard fault model are same as, both models offer testing of each and every components that are either stuck-open or stuck-short in digital test domain. Any element of the terminal of an analog circuit is not appropriately connected with the other circuits therefore; stuck-open fault is exposed. In addition, stuck-short fault happens if the short is produced among the terminals of the components in analog testing. On the contrary, if the transformation in a circuit occurs that do not have an effect on its connectivity and thus, resulting in the purpose of a circuit out of specifications referred by soft or parametric faults. The parametric faults are defined as the dissimilarity between the factors of parameters that are away from their acceptance boundary. Here in this article we are discussing the catastrophic or hard fault model. The fig 5 describes the fault model that is related with the resistors, capacitors and MOS field-effect transistors (MOSFETs). The stuck-short fault is imitated as the parallel resistor Rp whose value is 10 ? similar; stuck-open fault is imitated by the series resistor Rs whose value is 100 M?. In this article the above mentioned fault models are utilized by HISPICE simulations. Test Procedure Analog Integrated Circuits (IC) that is dissimilar to digital Integrated Circuits comprises of comparably less circuit primitives including amplifiers, comparators and many more from which testing is considered for many parameters. Designers specify the test parameters to gain, offset voltage, slew rate, bandwidth, signal to noise ratio and many more. In general, the testing of analog circuits is conducted on functions associated with specification of offset voltage, slew rate, bandwidth, signal to noise ratio etc., as the functional tests are also carried out on package tests and wafer levels. The main reason is absence of a standardized fault model for an analog circuit. The proposed testing procedure that is demonstrated in this paper incorporates stuck-open and stuck-short faults are initially injected at a circuit level. Likewise, the format of these faults is illustrated in HSPICE and is injected in nominal descriptions of the circuit. Moreover, by utilizing the HSPICE simulator, the momentary response is assessed along with the measurement of frequency and voltage outputs, as shown in Fig.7 demonstrates all the test procedures and steps in terms of a flow chart following OBIST approach. Furthermore, in the following paragraphs, different steps are demonstrated associated with each procedure Step 1 includes a fault free circuit that is converted in to an oscillator that is simulated, where the oscillation frequency and output amplitude signals are the outputs. Step 2 incorporates a list of faults that is extracted from the circuit netlist (CUT). Step 3 includes a generation of a faulty netlist via fault injection. Step 4 is a stage where a simulation is carried out to analyze the faults in CUT. The next step i.e. the 5th step is involved in the fault detection, as it is completed on the basis of faulty output calculations with parameters associated with fault free tests. Step 6 incorporates a repeatable procedure for injecting all the faults In step 7, a calculation of circuit fault coverage is carried out. Likewise, the implementation of a procedure is carried out by computer program coded in C language. Example Inverter and Oscillation-Frequency Calculation The OBIST anticipated a method for the calculation for an oscillation frequency by taking into consideration an inverter mentioned in fig 7 as an example. Here a couple of matching transistors i.e. n-channel MOS (NMOS) and p-channel MOS (PMOS) are joint together provided that the transistor gated are connected as input while the drains are connected as an output, to form an inverter that is called as COMS. It is compulsory to ensure that the PMOS device is broader than the NMOS in order to get the symmetric characteristics resulting in the increase in threshold voltage Vcc/ 2. Therefore, in order to attain the required threshold voltage the width of the PMOS device must be 2.5 times greater than the NMOS device. Here during constructing a CMOS inverter circuit to oscillate, the standard CMOS a stable-oscillator perception is employed. The R1 resistor of the CMOS inverter is connecting the output CUT and its input, therefore acting as dc negative feedback. Furthermore, the input of another inverter i.e. U1 is directly connected to the output of the CUT in fact, the input of the CUT is connected via capacitor to the output of the U1 thus resulting in a positive feedback. It is believed that there is no charge accumulation in the capacitor if the input of the CUT is zero and the output of the inverter U1 is low down. Since the input impedance related to the CMOS inverter is larger as, a result resistor R1 charges the capacitor. Now the output of the CUT go down to zero as soon as, the threshold voltage of the CUT increases, Vth(Vth = Vcc/2) resulting in the higher output of the U1. We know that the voltage of the capacitor is transversely constant therefore; the differentiation among the two sides of the capacitor must stay Vcc/2. To facilitate, if the capacitor of one side leaps to Vcc from zero then the other side must leaps to 3Vcc/2. The voltage Vcc/2 becomes visible on R1 and C1 because they are the common nodes however; the capacitor begins to discharge all the way through R1 this is because the other node of R1 is zero. Now at this point almost immediately when the voltage that is present near R1 reaches the threshold voltage Vth , the output of the inverter U1 set off to zero and the output related to the CUT transfers to Vcc. On this position the capacitor C1 begins to charge in the direction of Vcc because the common node voltage present at R1 and C1 is dragged to –Vcc/2. As revealed in fig 8 this cycle constantly produces square-wave output. The frequency of oscillation can be calculated as described below For the duration of given time interval t1, the voltage that is present near the capacitor C1 (vc) increase from –Vcc to Vth by considering that the output level is low. Now the frequency can be calculated by selecting R1=500 k?, C1 = 10 nF, and R2 = 5 M? therefore, the oscillation frequency is fosc= 90.9HZ. The oscillation frequency in HSPICE of the simulated frequency can be attained as fosc= 86.90HZ. The fault model for MOS transistors is represented in fig 9. The value for the corresponding resistor Rp is 10?, imitated as stuck-short fault whereas, the series resistors Rs that is imitated as stuck-open fault has value of 100M?. Stuck-open fault of PMOS transistors Qp is explained in fig 10 that shows the circuit configuration testing. Suppose if the input of U1 is +5V than the output will be zero. In the beginning C1 capacitor will set up to charge through the R1 until the threshold voltage of Qn becomes greater than the Vth. Therefore, Vds of Qn will become zero from Vds=Vgs-Vth because Qn is in service. After that the output related to the U1 turns higher and will continue to be high (+5V) since, Qn has no power on the output and the Qp drain is also disconnected. As illustrated in fig 12 (a) same results are obtained with the help of HSPICE. Subsequently now we discuss the stuck-short fault as illustrated in fig 11 of PMOS Qp. The output result will constantly be zero because; the input of U1 is shorted to Vcc. Similarly the same results can be obtained from HSPICE simulation, NMOS transistors Qn for stuck-open and stuck-short faults. Now the stoppage of the circuit oscillation can be performed by inserting any one of the faults into an inverter. If the inverter circuitry of any one of the transistors becomes short or open the resulting output will be higher or lower according to the inserted fault. As a result the simulation results agree with the hypothesis. In order to insert each and every fault first we have to connect the Rp or Rs than we will find the Qp or Qn from the netlist file of the oscillator. The syntax in the HSPICE netlist for the MOSFET element is Mxxx nd ng ns _nb_ mname __L =_length_ __W =_width_ The syntax for a resistor is Rxxx n1 n2 _mname__R =_resistance. For instance, to inject a stuck-open fault to Qp that is defined in the netlist as m1 inm in vccm vccm p w = 45 u l = 5 Faults Output voltage level (V) Output oscillation frequency (HZ) Rc, Cc open 2340700 Rc short 1960900 M2 open 5021600 M2 short 2440200 M1 open 2283900 M1 short 4973200 M5 short 2326400 Other faults No oscillations TABLE I (Simulation results for Op Amp) Faults Output Voltage level (V) Output Oscillation frequency (HZ) R1 open -0.077595,0.038166 743.98 R2 open -4.6736,4,6182 684.91 R3 short -4.6109,4,3127 3129.0 R4 short -0.018609,0.017040 8095.8 R5 short -0.58972,o.32922 9933.1 R6 open -0.33209,0.058148 9891.2 R6 short -4.5420,4.1179 314.57 R7 open -4.6559,4.6587 206.02 C1 open -4.5865,4.1690 15217 C1 short -0.00041846,0.0000010502 9996.8 C2 open -0.00052414,0.00042881 9979.2 Other faults No oscillations TABLE II (Simulation Results for Continuous Time state Variable Filter) By reading the net list file of the oscillator ‘m1’ is found from the file thus Rs is added as follows m1 ccm in vccm vccm p w = 45 u l = 5 u Rs inm ccm 100e + 6. Now after making necessary changes the faulty circuit is then simulated and the oscillation frequency as well as the signals of the output is monitored. In fig 12 all the faults that are inserted and the output signals related to the faults are explained. Chapter III: Simulation Results In analog and diverse signal environments, filters and Op Amps are mostly used. However, for testing them efficiently, filters are the core components, as they have a high value in the domain of analog systems. Moreover, the testing of circuit along with a method associated with oscillation, the initial step would the conversion of CUT in an oscillator by an addition of additional circuitry that can be considered as a feedback. In case of any fault in the circuitry, the converted circuit will oscillate or the frequency and voltage will have considerable changes, as compared to fault free conditions. Furthermore, few circuits associated with the mixed signal and analog benchmark circuits are given consideration in the investigation demonstrated in this paper. Compensated CMOS Op Amp As demonstrated in Fig 1.3, the compensated CMOS Op Amp is tested. Likewise, for testing the Op Amp circuit, the first step will be to transform it into an oscillator via addition of negative and positive feedbacks, as shown in Fig 14. Likewise, the Op Amp circuit has been modified in a second order system that has probable features or characteristics associated with oscillation. Moreover, the open function called as the open loop transfer is demonstrated in Figure below: In a fault free environment, the frequency of oscillation along with the output voltage levels is illustrated as: fosc = 1.9598 MHz and Vout = _?4.6676, 4.8642_ V, correspondingly. In this scenario, consideration is given to only catastrophic faults. Likewise, Table 1 demonstrates results extracted by HSPICE simulation. Moreover, it is evident now that the output frequency expressively deviates with any vaccinated fault. However, frequency measurements are not able to identify short-at compensator resistor Rc. Therefore, by examining voltage and frequency measurements, 100% high voltage coverage is achieved. Continuous-Time State Variable Filter The consideration of the second circuit that is utilized for illustrating the testing methodology is comprised of a variable filter that is continuous-time. Likewise, this specific variable filter that is also called as a universal filter is achieved from the mixed and analog signal benchmark circuits. As illustrated in Fig. 15, the schematic figure of active filter deployment by incorporating three Op Amps. It includes bandpass, low pass and high pass filters capable for giving outputs that are recognized as BPO, HPO and LPO separately. The conversion of the circuit is transformed in to an oscillator for simulation that is the second part of the process. Deprived of any loss of generalization, the circuit is utilized as a low pass filter. Hence, the procedure of defect-detection is applicable on the calculated signals set as LPO. Likewise, it is a conventional approach, as the contemplation of BRO and HPO can hypothetically augment the sensitivity of defect-detention that is caused by increase in observation. The following three questions demonstrate the transfer functions in three respective equations i.e. high pass, low pass and bandpass: The component values that are achieved from the benchmark circuit specifications are as follows: R1 =R2 = R3 = R7 = 10 k?,R6 = 3 k? R4 =7 k?, and C1 = C2 = 10 nF. Moreover, under fault free environment, the oscillation frequency and voltage levels are examined as fosc = 789.66 Hz; Vout =_?4.5476, 4.2384_ V. Furthermore, to test associated filters, the entire Op Amps are identified as ideal. Although, Table II simulation results concluded that almost all faults are identified and detected via this methodology. Faults Output Voltage Level (V) Output Oscillation Frequency (Hz) R1 Short 5.2753, 4.9536 1447.6 R2 Short 5.2753, 4.9536 1447.6 C2 Open 4.6229, 4.8767 984.37 Other Faults No Oscillations Table III (Simulation Results for VCVS Filters) Voltage-Controlled Voltage Source (VCVS) Filter The testing method is validated and demonstrated on a Voltage-Controlled Voltage Source (VCVS) Filter. Likewise, the VCVS filter is a distinction of the Sallen key circuit. Likewise, the Sallen key surface is replaced with an amplifier that is non-inverting and with a gain larger than unity. Moreover, the presence of a VCVS is found in many circuit realizations such as high pass, low pass and band pass filters. The outputs results of the Op Amps resistors establish an amplifier that is non-inverting that cascades to constructs high order filters. After the construction, the specific filter sections are not similar to each other. Likewise, each section of the filter demonstrates a quadratic polynomial comprising of the nth-order polynomial explaining the overall filter. The paper highlights the consideration of a bandpass VCVS filter, as demonstrated in Fig 1.6. Moreover, the centralized frequency of VCVS bandpass filter is illustrated by: Furthermore, by examining the parameters via following values i.e. R1 =R2 = R3 = 20 k? and C1 = C2 = 20 nF. Likewise, the centralized frequency is calculated as f0 = 562.69 Hz with the gain of the filter value K ? 2.5. By selecting the adequate value of K (K = 2.500855), the transfer function poles are forced to j?-axis associated with the s-plane. Accordingly, the oscillation frequency related to the oscillation frequency of the VCVS filter accomplished by simulation = 560.99 Hz. Moreover, the amplitude range is from _?0.0011843, 0.0021159_V. Fig 17 shows the output of the VCVS filter that is in oscillation model and Fig 18 demonstrates the output in test mode with R2 that is an injected open fault. The fault coverage in this scenario is 100%. Detailed simulation results are illustrated in Table III. Faults Output Voltage Level (V) Output Oscillation Frequency (Hz) R1 Open 4.5310, 4.6894 14805 C1 Short 4.5234, 4.2553 16779 R3 open 4.4884, 4.8268 4278.7 R3 Short 0.0017175, 0.00012047 100840 Table IV (Simulation Results for Notch Filter) Field-Effect Transistor (FET) This part of the paper illustrates the procedure to test a FET that will follow oscillation test methods. Likewise, for performing a test on a transistor, a construction of oscillator circuit along with a transistor is required. A phase-shift oscillator will be incorporated in this scenario, as it constructs positive feedbacks by utilizing inverting amplifier along with adding 180 phase shifts that is associated with high pass filter circuits, as illustrated in Fig 19.likewise, it constructs 180 phase shifts by only a sole frequency. For imposing the circuit in to oscillation, number of phase-shifts circuits will construct adequate phase shift and gain. Moreover, the FET gives the output of a negative gain along with a 180 phase shift and for every RC pair, 60 phase shifts can be achieved. Moreover, there is a one third loss in signal quality level, and therefore minimum requirements for a gain that is required for the compensation of the active element for the loss is 27. AS the frequency of oscillation is calculate via: The capacitors and resistors are donated by 10 k?, C = 6.5 nF, Rd = 10 k?, and Rs = 3 k?. Likewise, the oscillation frequency is computer via fosc = 999.6 Hz. The circuit seizure halts the oscillation process by injecting the faults in FET. Moreover, if the FET cannot make any contact with the circuit and is considered as disconnected, the circuit does not oscillate. However, the injection of the short faults in the circuit enables FET operations in the cut off region, as demonstrated in Fig 20. Faults Output Voltage Levels (V) Output Oscillation Frequency (Hz) R2 Open 6.8844,6.6512 956.40 R3 Open 6.5409, 6.1659 991.36 R4 Short 7.1448, 5.8759 975.68 R5 Open 5.9213, 5.3756 1166.9 R7 Short 4.3850, 4.4082 3165.1 R8 Short 1.4850, 1.5946 4143.2 R9 Open 0.52000, 0.79886 6039.3 R10 Open 12.983, 11.136 1106.2 R11 Short 1.2033, 1.1957 3836.9 R 12 Open 8.4403, 7.9554 780.56 R 13 Open 5.4342, 2.5190 1004.5 C1 Open 2.3735, 2.3349 1513.3 C4 Open 1.8255, 1.9589 1653.7 Other Faults No Oscillations Table IV (Simulation Results for Leap Frog Filter) Notch filter As illustrated in fig 21 the notch filter is a device that is used to filter any particular frequency from an input signal. This is a extremely suitable narrow frequency band-reject filter to clean polluted signals when the intervention drops inside the bandwidth. The transmit function of the classic notch filter, if the input is denoted by y (t) and the output of the notch filter is denoted by h (t) is mark as: The Op Amps are considered to be the best because it is common in a lot of cases for filters. By using this 100% faults can be detected. The 100% faults in real cases are not 100% ideal thus providing an acceptable variety of testing effectiveness. The frequency of oscillation that is attained by simulation is 4119 HZ, in addition the range of the amplitude is table 5. Hence by utilizing notch filter 100% faults are detected that are inserted and 100% fault coverage is attained. Leapfrog filter Another circuit that is utilized for testing mixed-signal and analog circuits is defining as a leapfrog filter mentioned in fig 22. The benefit of using this leapfrog filter is that the faults occur because of the element values and Op Amps are circulated across the filter instead of being concentrated in the specific biquad. As a result, it makes them more robust. The leapfrog filters are maintained by the filter solutions for the low-pass and the band pass of all pole designs. The capacitors and the alternating inductors are substituted by the positive and negative gain integrators. In order to maximize the performance, the filter solutions utilize positive Miller integrators for positive gain integrators. A feedback and feed forward resistor is included in each integrator output. The resistors are placed in parallel format in the starting and ending of each integrator, with the capacitors that simulates the passive-termination resistors. The following equation is used to calculate the oscillation frequency The resistor and capacitor for this filter are selected as Ri = 10 k?, for i = 1–12, and C1 = C4 = 0.01 ?F, and C2 = C3 = 0.02 ?F. Then, the frequency of oscillation of the fault-free Oscillator is calculated as fosc = 1.174 KHz. The output of the faulty leapfrog filters and fault-free filters are illustrated in figs 23 and 24. Table 5 explains the simulation results associated with the leapfrog filter. Chapter IV: Conclusion This study demonstrates the deployment of OBIST methods and techniques for testing mixed signal and analog part circuits. In summary, an OBIST methodology does not have a requirement of stimulus generators and complex analyzers, as they have gained and incorporated for testing mixed and analog signal circuit integrated with SOC environments. Moreover, disastrous faults are addressed in the study along with comprehensive simulation results carried out on mixed and analog signal benchmark circuits. Furthermore, other circuits are also analyzed and examined for evaluations and covering faults along with a demonstration of OBIST methods, as they are capable of provisioning high fault coverage with efficiency, as there is low area overhead. Read More