Operational Amplifier Design - Case Study Example

RUNNING HEAD: OPERATIONAL AMPLIFIER NAME TUTOR’S NAME INSTITUTION DATE Operational amplifier design Abstract The main of this report is to provide a detailed description of the design of an operational amplifier which has been set up to meet some certain specifications which are already provided. Basing the paper on the given specifications, the circuit topology of the standard operational amplifier has been chosen this is due to the fact that the given topology can be able to give out the given required design. The specifications which have been presented in this report have been compared to computer simulations from pspice or any other circuit simulator like hspice. Introduction Operational amplifiers form some of the basic building blocks of the common electronics circuits and systems that are in existence today. They form some of the basic parts of the analog systems and systems which produce mixed signals. In their differing forms, the operational amplifiers are used to make a reality of some of the crucial achievements of the electronic industry including: - biasing DC voltages and achieving the bias, high gain amplifications, filtering, analog to digital conversion amongst others. There are many challenges which are posed by the design of some amplifiers mostly due to scaling down of the channel lengths of the transistors and the supply voltages which occur at the generation stages of the operating amplifier. A basic operational amplifier has single or more differential phases. It is followed by some additional phases for gains which depend on the requirements of the amplifier. In this paper, it is a detailed discussion of the design of a three stage amplifier. The paper has some detailed specifications of the circuits and the basic topology of the operational amplifier. The procedures for the design and some examples of the use of the given technology have been included in the paper so as to have an all inclusive and fully specified operational amplifiers. Definitions for the specifications CMRR: stands for “common mode rejection ratio”. This is the ratio of the common mode gain to the differential gain. Power dissipation: the total power that is dissipated. It is the circuit’s voltage and current product. Open loop gain: the ratio between output voltage and the differential output voltage. It is also referred to as the “large signal voltage gain” as the output is always larger than the input. Slew rate: maximum value of change in output voltage per a unit of time. Overshoot: maximum value in which the device deviates from the steady value Operation of the circuit The following is an integrated circuit of a basic amplifier. The different amplification stages have not been subdivided though a discussion of the parts will be given in details. The topology which has been indiccated in the above figure is a standard operational amplifier. The subsections in the diagram are the gain stages and the bias phase. The topology above, upon further examination of the sub sections and the phases will be seem to adhere to all the design specifications which are given. Design of an operational amplifier Operational amplifiers are part of the variety of building blocks that make up the basic components of analog circuits in the world of electronics. They are linear devices which have almost all properties that are requisite for ideal direct current amplification. They are thus mostly used in signal conditioning, mathematical operations e.g. add, subtract, integrating and differentiating and also are used for filtering. A basic operational amplifier is a device which has three terminals. Among the three terminals, there are two inputs which have high impedance. One is the inverting input, with a negative sign and the non-inverting input with a positive sign. The third terminal is the output of the operating amplifier. It can be used to either sink voltage or current or source them. In a linear op amp, the signal in the output is the factor for the amplification which is achieved by the device (This factor is called the “amplifiers gain (A)”) multiplied by the signal at the input. The nature of both the input signal and the output signal gives chance to have four different classes of the “operational amplifier gain”. They include: - Voltage gain: voltage in and voltage out Current gain: current in and current out Transconductance gain: voltage in and current out Transresistance gain: current in and voltage out The difference between the input signals which are applied is the amplified output of the operational amplifier. The output signal is differential between the inputs and thus the input of an operational signal is thus a differential amplifier. At this stage, the paper will take a step by step design of the amplifier. Differential amplifier The diagram below is a general form of a differential amplifier: - The amplifier has two inputs V1 and V2. Transistor T1 and transistor T2 are biased at the same point of operation. Their emitters are commonly connected. Resistor Re returns them to the common line Vee. +Vcc and –Vee are dual supplies which ensure that the supply is constant. Considering that the two inputs are in anti phase, the output voltage Vout is the difference between them. The “common mode rejection ratio” is a measure of the tendency of the amplifier to reject common input signals from the two inputs. A high value of the CMRR is good for those applications which have a small difference I their voltages. The value of the CMRR in db is given by: - A=20*log (Vo/Vi) The CMRR can also be given by the ratio of the differential to the common mode gain and given in decibels (db). CMRR = 10log (Ad/A cm) 2 = 20 log (Ad/A cm) Where: Ad = differential gain and, Acm = common mode gain. In this case, the differential amplifier in the circuit will have a CMRR of 40db V in of 1.0 *10 -3 Vrms So; 40db = 20 * log (Vo/Vi) = 20 * log (Vo / 1.0 *10 -3 V) = 20* log 1000Vo Log 1000 Vo = 2 Differential gain stage In the first diagram, this stage is composed of transistors M1 to M4. M1 and M2 are made of “N channel MOSFET (NMOS)”. These are the basic inputs of the transistor. The inverting input is made from the M1 gate whilst the gate of M2 comprises the mom inverting input. When a differential input is applied across the two inputs as described above, the final output is an amplified signal of the input in accordance to the gain of the amplifier as at the differential stage. The gain at this stage is gotten from the transconductance of M2 multiplied by the total resistance which happens to drain at M2. The main resistances that make a contribution to the output resistances are those that belong to the input transistors also for the transistors M3 and M4 which are the “active load transistors”. There is a “current mirror active load” which has been used in the circuit and it has some distinct advantages; when active load devices are used, the output resistance is large in a relative minute size of the “die area”. The topology for the current mirror is responsible for converting the input signal from the differential mode to the single ended mode. This load also assists with the value of the” common mode rejection ratio” Second gain This helps in the provision of the second gain to the amplifier. It is made up of transistor M5 and transistor M6. In this stage, the output which results from the transistor M2’s drain is taken and then amplified through transistor M5. This transistor has been put in a standard “common source configuration”. In this stage, just like in the previous differential stage, M6 which is active is used as the load resistor for transistor M5. The gain which is achieved at this stage is the transconductance of transistor M5 multiplied by the load resistance which is made up of the output resistances from both M5 and M6. Bias The bias of this operational amplifier is achieved by the use of four transistors. M8 and M9 comprise a straightforward “current mirror bias string” which is used to supply a voltage between the gate and the sources for both M6 and M7. The transistors M6 and M7 sink some certain amount of current which is based on their gate so as to source some voltage that is controlled by the “bias string”. Transistors M8 and M9 are connected to diodes in order to make sure that they are operating in at the saturation region at all times. When all the other transistors in the circuit are properly biased, the node voltages which happen to be present at the circuit are used to control the circuit. Third order low pass filter This filter receives the input from the differential amplifier and feeds the voltage to current converter. Voltage to current conversion The following circuit can be fixed at the output voltage to allow standard conversion. The input voltage is from the amplifier. It has been calibrated to adhere to the specifications. Standard current at 0% to 100% is 5mA to 25mA on a range of o to 1mV rms. At 1mV the resistor will have a voltage applied to it which will result in 25mA current. The resistor (250 ohms) is the one that is used to establish the relation between the input voltages from the amplifier to the output current. The precision of the resistance is determined by the value that is desired. Design of the operational amplifier In the design of the amplifier, the first step to be considered is to get the details of the required specifications. These details will be based on the discussed standard topology which necessitates a simpler design of the operational amplifier. This circuit can also be called a transconductance amplifier. Procedure to follow The amplifier uses a tsmc 0.25um technology. a) I6 will be a value determined by the power dissipation and the slew rate = 50uA b) Compensation capacitor, Cc = 16/slew rate = 2.5pF c) Get gm1 ; from the gain bandwidth = 502 uA/V d) Get gm5 ; from stability condition = 107 uA/V e) Get Av f) Get I7 g) Get (W/L) 1,2; =31, W/L)5 = 20, W/L)3,4 = 1.5, W/L)6 = 2.5, W/L) 7 = 27 When all the connections are properly fixed, all the transistors should be in saturation. A DC simulation should assist in checking the transistors dynamic range. This should be optimized to achieve linearity. Taking the output voltage as 1mV, the output swing of the current loop should fall between 5 and 25mA. Fix the voltage at the DC input for maximum output. Voltage of the output at the differential amplifier should match the following stages. When the circuit is simulated and does not meet the specifications, further iterations should assist in achieving the desired specifications. Some of the iterations are; Fixing the gain: if the required gain is not met, the width of the input transistors is increased till the required value is met Simulations and the results Final results verification is done using a pspice simulator. All the results of the simulation are then compared to the specifications of the operational amplifier. Net list of the op amp “ Vbias vdd 0 dc=2.5 M9 net47 net47 vdd vdd pch w=5u l=2u M8 (net47 net47 0 0) nch w=3.5u l=2u M7 (net55 net47 0 0) nch w=3.5u l=2u * DIFFERENTIAL INPUT THROGH Vp and Vn M2 (net53 Vp net55 0) nch w=60u l=1.15u M1 (net56 Vn net55 0) nch w=60u l=1.15u * OUT PUT OF THE OPAMP IS THROUGH VOUT M5 (Vout net53 vdd vdd) pch w=100u l=1u M6 (Vout net47 0 0) nch w=32.5u l=1u M3 (net53 net56 vdd vdd) pch w=6u l=2u M4 (net56 net56 vdd vdd) pch w=6u l=2u * CL IS LOAD CAPACITOR AND CC IS COMPENSATING CAPACITOR CL (Vout 0) 20p CC (net53 Vout) 4p .end” Performance specifications Specifications are tested to ensure that the operational amplifier meets the standard of the requirements. The results of the simulation are compared with the operational amplifier specifications. Due to the low power, the slew rate was a bit distorted. Discussion of the simulation The results of the simulation were positive as the specifications were all in line. The topology that has been used is both advantageous and disadvantageous. It has however got the ability to meet all desired specifications. The topology has the advantage of a large gain. If the open loop gain of the op amp is measured, the graphical results are as obtained below. The slew rate of this topology has been affected by the difference in the parameters, the phase margin and also the drain current. The slew rate alters the settling time. A standard op amp should achieve the settling time specifications in such a design. The slew rate is also limited by the amount of current that the specifications’ power dissipation allows. Conclusion The design specifications of the operational amplifier above can be tested to precision in a lab. The three stages have been clearly defined and the outcome of the simulation has been indicated to demonstrate the workability of the circuits. All the used devices are locally available in electronics outlets. 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