Literature review of Analog Circuit Computer Aided Design - Essay Example

--------------------------- --------------------------- --------------------------- --------------------------- Literature Review of Analog Circuit Computer Aided Design (CAD) Introduction The main purpose of this research of "Analog CAD" is to get the values of transistor sizes and components values like resistors and capacitances if the analog circuit specification is given. The optimization technique it adopts is geometric programming (Boyd, 2004). Till today analog circuit design automation is done for long length transistors or sub-micron transistors. Main objective of this research work is to automate circuit in deep sub-micron region. Before starting actual work on any topic it is necessary to go through literatures otherwise one may land up in a result which has already been found out by some other person. Review of Literature This section deals with the existing literatures related to analog circuit optimization. It outlines a summary of all the resource materials, authorial credentials, content credibility, source credibility, text credibility- Fluid integration of the source evaluation. A true literature review gives the proper sense of works that technology has achieved till date into that specified topic which helps one researcher to bring down his own research problem. Han Young et al. (1990) developed an analog silicon compilation system for CMOS op amps (OPASYN). The synthesis starts from a certain specification. From its database, program selects op amp topology that suits most with the given specification. Using parametric optimization the circuit then determines optimal value for its parameters. It also produces Design-Rule-Correct compact layout of the optimized op amp. Yang et al. (1995) proposed a Simulated Annealing (SA) algorithm for topology selection and sizing. In analog cells, topology choice and sizing simultaneously is efficient than normal two step mode synthesis. Basic problem with that approach is that super circuits must be worked out for each sort of analog cells. Chen et al. (2000) placed an iterative optimization idea for improving delay in digital circuit. Instead of only adjusting that gate sizes to reduce delay, they adjusted wire loads of the gates by repositioning them using geometric program. It gave better result in deep sub-micron design where the effect of interconnect delays dominates Mandal P and Visvanathan V (2001) devised an efficient technique for sizing of op amp by sequential convex optimization problem. This method then prototyped in MATLAB to apply into CMOS two stage op amp. Paper mostly focuses on long length transistor. In short channel case results did not come satisfactory due to second order effects. To overcome this, model was used that gave acceptable result.. Hershenson M et al. (2001) also worked on same topic and came out with fruitful result. There they have used 0.8 technology. Dawson et al. (2001), using geometric programming optimized the allocation of local feedback loops in a multistage amplifier. In a multistage amplifier local feedback loops effects its overall bandwidth, gain, rise time, noise and linearity. Using GP tool these problems had been solved taking into account wide variety of constraints. After that, Daems et al. (2001) came with simulation based automatic generation of signomial and posynomial models that can be used for analog design automation. These posynomial models were found to be more useful for geometric programming optimization. There, they tested the methodology with a CMOS OTA in 0.7 m technology. Hershenson M. (2002) presented a technique for the design of Analog- Digital Converter (ADC). In a predefined pipeline ADC topology she tried to get the component values and transistor sizes meeting the specification and keeping constraints like power, SNR, sampling frequency and area in convex form. Eackelaert et al. (2003) depicted a new technique to generate symbolic expressions for the performance characteristics. The technique determines the coefficients and the exponents of a posynomial template based on performance data extracted from numerical simulations. They did the experiment with a high speed CMOS operational transconductance amplifier in 0.7 micron technology. Transistor sizing of nanoscale CMOS inverter had been performed by Pattanaik et al. (2003). They started with modified I-V model and formulated geometric problem that works well up to 10 nm. Their method also computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. Its accuracy had been verified in 250nm process. The extended version of that work predicted that same for 50 nm CMOS inverter. In 0.18 m technology and 1.8 V CMOS process Phase Locked Loop circuit automation was done by Colleran et al. (2003). Their result include a 1.9 GHz PLL with a period jitter of 2.2ps RMS and an accumulated jitter of 6.2ps, consuming 10.8mW. Another work of Pattanaik M and Banerjee S, (2003) is regarding power delay optimization in sub-micron and deep sub-micron CMOS inverter. Verification is done with 0.25 m technology but with the extended approach result was satisfactory for length 0.09 m too. Jaskirat et al. solved the gate sizing problem employing an ellipsoid set as a bounded variation model. It also considers the spatial correlations of the intra-die parameter variations. The original set of posynomial delay constraints are modified and converted to another set of posynomial constraints and after the resulting robust GP is efficiently solved. Gate-size optimization for noise reduction was carried out by Sinha D and Zhou H, (2006) ensuring that it is meting the timing constraints. First gate-size optimization under coupling-noise and timing constraints was formulated, and then it broke down into two sub-problems of gate-size optimization under noise and timing constraints, respectively. The gate-size optimization under noise constraints is solved as a fix point computation Conclusion Hence it can be inferred that all the works done in the specified field are either for long length transistors or sub-micron but in deep sub-micron region (nano scale) this problem has not been formulated yet. So, working on the topic will give a lot of scope and well framed credit. References 1) Boyd Stephen. "Convex Optimization". Cambridge University Press. 2004 2) Koh H. Young et al. "OPASYN: A Compiler for CMOS Operational Amplifier". IEEE Transactions on Computer-Aided Design. Vol. 9. No. 2. 1990 3) Toumazou Christofer et al. "Analog IC Design Automation: Part I- Automated Circuit Generations: New Concepts and Methods." IEEE Transactions on Computer-Aided Design. Vol. 14. No. 2. 1995 4) Yang H. Z et al. "Simultaneous Topology Selection and Sizing for Synthesis of Analog Cells". IEEE .1995 5) Harshenson M. et al. "GPCAD: A Tool for CMOS Op-amp Synthesis". ICCAD. 1998. 6) Harshenson M. et al "Automated Design of Folded-cascode Op-amps with Sensitivity Analysis". IEEE, 1998. 7) Cheng et al. "Simultaneous Gate Sizing and Placement". IEEE Transactions on Computer-Aided Design. Vol. 19. No. 2. 2000 8) Dawson Joel et al. "Optimal Allocation of Local Feedback in Multistage Amplifiers via Geometric Programming". IEEE Transactions on Computer-Aided Design. Vol. 48. No. 1. 2001 9) Hershenson M. "Optimal Design of a CMOS Op-amp via Geometric Programming". IEEE Transactions on Computer-Aided Design. Vol. 20. No.1. 2001 10) Mandal P and Visvanathan V. "CMOS Op-amp Sizing using a Geometric Programming Formulation". IEEE Transactions on Computer-Aided Design. Vol.20. No. 1. 2001 11) Daems et al. "An Efficient Optimization-based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits". DAC. 2002. Read More