Error Simulation Enviroment For The Dicode Pulse Position Modulation - Essay Example

CHAPTER SEVEN ERASURE AND ERROR SIMULATION INVIROMENT FOR THE DI PULSE POSITION MODULATION SYSTEM WITH REED SOLOMON Introduction In this chapter, three test bench environments: erasure only, error only, and erasure and error would be applied on the designed system, chapter 6. A Modelsim_Altera version (6.5b) software is to be used to simulate the system. The system has shown that it has the ability to detect, correct erasure, and error symbols when they overcome its limitation. 2. Erasure Only Test Bench A VHDL test bench program Apendix ( ) was built to provide an environment where erasure errors can be injected into the system. According to equation (6.8), the designed system can correct up to 8 erasure errors only. Above this number, the system will fail to decode the original message. Figure 7.1 shows the flowchart for the erasure only test bench. The following two test scenarios are likely to take place: 2.1. Correctable codeword The number of erasure error symbols that is erased is within the capacity of the decoder in his recovery of the original data. In this test design, the number of erasure error symbols must be less or equal to 8 symbols per codeword. Figures (7.2) & (7.3) show the system input/output signals. Figure (7.2) shows the performance of the system when the number of erasure symbols equal 8 per codeword, while the figure (7.3) displays the system signals when the number of erasure symbols equal 5. In these figures, the fail output signal is logic 0. This means that the system has successfully decoded the original codeword. We can add or delete erasures by updating lines 294 and 295 inside the code. Figure 7. 1. Erasure only test bench flowchart 2.2. Uncorrectable codeword The number of erasure error symbols that is erased is greater than the capacity of the decoder to recover the original data. In this test design, the number of erasure symbols is greater than 8 symbols per codeword. Figure (7.4) shows the system input/output signals when the number of erasure symbols equal 9 per codeword. In this figure, the fail output signal is logic 1, which means that the system has failed to decode the original codeword. We can add or delete erasures by updating lines 294 and 295. Figure 7. 2 System input/output signals with 8 erasure symbols Figure 7. 3 System input/output signals with 5 erasure symbols Figure 7. 4 System input/output signals with 9 erasure symbols 3. Error Only Test Bench A VHDL test bench program Apendix ( ) has been built to provide an environment where errors can be injected into the system. According to equation (6.7), the designed system has the ability to correct up to 4 erasure errors only. Above this number, the system will fail to decode the original message. Figure 7.5 shows the flowchart for the error only test bench. The following two test scenarios are likely to take place: 3.1. Correctable codeword The number of error symbols is within the capacity of the decoder to recover original data. In this test design, the number of error symbols must be less or equal to 4 symbols per codeword. Figures (7.6) & (7.7) show the system input/output signals. Figure (7.6) shows the performance of the system when the number of error symbols equal 4 per codeword. The figure (7.7) displays the system signals when the number of error symbols equal 2. In these figures, the fail output signal is logic 0. This means that the system has successfully decoded the original codeword. We can add or delete errors by updating line 295. 3.2. Uncorrectable codeword The number of error symbols is greater than the capacity of the decoder to recover the original data. In this test design, the number of error symbols is greater than 4 symbols per codeword. Figure (7.8) shows the system input/output signals when the number of error symbols equal 5 per codeword. In this figure, the fail output signal is logic 1 which means that the system has failed to decode the original codeword. We can add or delete errors by updating line 295 inside the code. Figure 7. 5. Error only test bench flowchart Figure 7. 6 System input/output signals with 4 error symbols Figure 7. 7 System input/output signals with 2 error symbols Figure 7. 8 System input/output signals with 5 error symbols 4. Erasure and Error Test bench A VHDL test bench program Apendix ( ) has been built to provide an environment to inject erasure and error symbols into the system. According to equation (6.10), the designed system has the ability to correct up to 4 erasure and 2 error symbols only. Above this number, the system will fail to decode the original message. Figure 7.9 shows the flowchart for the erasure only test bench. The following two test scenarios take place: 4.1. Correctable codeword The number of error symbols is within the capacity of the decoder to recover original data. In this test design, the number of error symbols must be less or equal to 4 erasures and 2 error symbols per codeword. Figure (7.10) shows the system input/output signals. In this figure, the fail output signal is logic 0 which means that the system has successfully decoded the original codeword. We can add or delete erasures and errors by updating lines 295 & 299 inside the code. 4.2. Uncorrectable codeword The number of error symbols is greater than the capacity of the decoder to recover the original data. In this test design, the number of error symbols is greater than 4 erasures or 2 error symbols per codeword. Figure (7.12) shows the system input/output signals when the number of error symbols equal 3 per codeword, while the figure (7.13) shows the system performance when the number of erasure symbols exceeds the system capability. In these figures, the fail output signal is logic 1 which means that the system has failed to decode the original codeword. We can add or delete erasures and errors by updating line 295 & 299 inside the code. Figure 7. 9. Erasure and error test bench flow chart Figure 7. 10 System input/output signals with 4 erasure and 2 error symbols Figure 7. 11 System original codeword Figure 7. 12 System input/output signals with 4 erasure and 3 error symbols Figure 7. 13 System input/output signals with 5 erasure and 2 error symbols 5. Conclusion Read More