The Fabrication Of Bipolar Junction Transistors By Diffusion Planar Process - Lab Report Example

? THE FABRICATION OF BIPOLAR JUNCTION TRANSISTORS BY DIFFUSION PLANAR PROCESS INTRODUCTION The fabrication of Bipolar Junction Transistors (B.J.T by the Diffused Planar Process is the objective of this report. The diffused planar process is self-explanatory in itself by the name. “The diffusion method for manufacturing junction transistors, pioneered by C. A. Lee at Bell Labs, uses a vapour of the impurity atoms surrounding the semiconductor material as it is heated, so that impurity atoms can diffuse in to the crystal lattice of the semiconductor. Thus, a region of N or P type semiconductor can be diffused into a block of pure intrinsic semiconductor, or (if the concentration is large enough) can change an existing N-type into P-type (or vice-versa) by providing more sources of holes than electrons.”[1] The use of SiO2 on the silicon substrate ensures isolation of the P and N regions and that the impurities don’t diffuse into the areas and therefore leads to the formation of well-defined P and N regions on the wafer.[6] Given below is the diagram of cross-section of a NPN transistor: Figure 1: Cross-section of a n-p-n BJT [7] The fabrication of BJT comprises of various sub-steps like RCA (Cleaning Process), Thermal Oxidation, Photolithography, Diffusion, Metallization, Alloying Process etc. [5] The process of fabrication starts by cleaning the substrate of impurities by the RCA procedure followed by developing a layer of SiO2 on the planar surface by the process of oxidation. The wafer is then coated with an appropriate photoresist material and developed by exposure to UV through base mask (mask #1). [6] After sufficient time of exposure, the SiO2 is removed by etching out from the region of base-diffusion followed by cleaning away the covering of the remaining photoresist coating. [6] The P-type base i.e. Boron is diffused into this region followed by re-oxidation to develop the layer of SiO2. [6] Next, by the process of Photolithography, the oxide layer is stripped off from the regions of collector and emitter by mask #2 and Phosphorous (N-type) is diffused on it. [6] The entire sample is re-oxidized and once again coated with the photoresist material and developed. [6] The substrate is then exposed to vapors of Aluminum which are allowed to condense upon it. [6] The excess Aluminum on the substrate i.e. at non-contact regions is removed chemically by ‘lift-off’. [6] The final step in the process is alloying of the contacts. [6] RCA Dust, SiO2, oxides and metallic contaminants are removed. [5] Consequently, the process has three chief procedures namely the Organic Clean, the Oxide Clean and the Ionic Clean. [5] “The RCA clean procedure should be performed immediately prior to any crucial step, especially those involving high temperatures.”[2] The RCA clean procedure consists of the following steps: Mixing of Organic, Inorganic and Oxide Stripping Solution 1. The Organic Solution is prepared by adding 1000 ml of H2O to 200 ml H2O2 and 200 ml of NH4OH. Heat the solution for 15 min at a temperature of 80 °C. [2] 2. The Ionic Solution is prepared by adding 1000 ml of H2O to 200 ml H2O2 and 200 ml of HCl. Heat the solution for 15 min at a temperature of 80 °C. [2] 3. The Oxide Stripping Solution is prepared by adding 2000 ml of H2O to the polypropylene vat. Add 40 ml of HF acid into it. [2] Bubbler Rinse Set-Up The bubbler rinse station is filled with deionized water and nitrogen is bubbled in it. [2] Organic Clean This step removes dust, grease and other organic impurities from the substrate. The substrate is submerged in the Organic Solution for 15 min and then placed in the Bubbler Rinse Set-up for 5 min. [2] Oxide Clean This step removes SiO2 from the substrate. The substrate is submerged in the Organic Solution for 15 min and then placed in the Bubbler Rinse Set-up for just 30 secs. [2] Ionic Clean This step removes metallic contaminants from the substrate. The substrate is submerged in the Organic Solution for 15 min and then placed in the Bubbler Rinse Set-up for 5 min. [2] Transportation of Wafers The wafers are carefully transported in a Teflon carrier so as to prevent re-contamination. [2] Drying The substrate is dried in a dryer set at optimum temperature. [2] THERMAL OXIDATION The process of oxidation of the Silicon Substrate to develop a layer of SiO2 can be brought about by either the ‘Dry’ or ‘Wet’ Thermal Oxidation. [6] Due to high energy consumption of the ‘Dry’ Oxidation, ‘Wet’ Oxidation is generally preferred to it. We too are going to develop the SiO2 layer by the Wet Oxidation process. The chemical equation governing the ‘Wet’ Oxidation is as follows: (WET) [6] For every 1 µm of SiO2 produced, 0.45 µm of Silicon is consumed. [5] Hence, to determine the oxidation conditions, by the chemical kinetics of the governing equation, the following parabolic relationship was determined: [6] Where: Xo = oxide layer thickness [?m]. t = oxidation time [hr]. B = parabolic rate constant [(?m)2/hr]. B/A = linear rate constant [?m/hr]. The apparatus for thermal oxidation consists of a quartz oxidation boat where the samples are loaded on and placed in the center of the quartz oxidation reactor. [6] Oxygen gas is set to flow at the rate of 8L/min at a temperature of 1100 ?C through a heated (96-100 ?C) saturator filled with de-ionized (DI) water and is then piped through to the reactor input tube where oxidation occurs. [6] Figure 2: The Thermal Cycle of the Wet Oxidation Process [4] The process of thermal oxidation is advantageous to the entire fabrication process as it provides excellent insulation, surface passivation and junction isolation and high breakdown voltage and masks most common impurities. [5] PHOTOLITHOGRAPHY The aim of photolithography is to selectively expose a region of the sample to further fabrication processing but rendering the unwanted regions unaffected by it. [6] The process of photolithography employs Photoresist (PR), a polymer substance light-sensitive, acid-resistant organic polymer, initially insoluble in the etching solution but on exposure to UV the exposed areas become soluble. [5-6] The regions which are to be selectively coated with the Photoresist are ‘masked’ with a featured glass and then subjected to UV. [5] The diagram given below pictorially elicits the process of photolithography. Figure 3: Photolithography [5] The next procedure after photolithography is the etching of SiO2. [5] The process of etching can be done in two ways i.e. Dry etching/plasma etching and Wet etching. [5] Dry etching/plasma etching is done by making an etch gas like the CFCs to break down and ionize i.e. form plasma under the effect of a high electric field in a low pressure chamber. [5] The free electrons are released in the plasma formation from the cathode where the Silicon substrate is kept. [5] The anions are bombarded on the cathode and the Silicon gets etched in the selected regions. [5] Wet Etching is done by dipping the substrate in the etchant solution or by spraying the etchant solution on it. [5] The most common etchant solution is NH4F:HF (7:1) [4] SiO2 + 6HF = H2SiF6 + 2H2O [5] After the process of photolithography and etching, the substrates are ready for the process of diffusion. DIFFUSION The process of doping is done by the Diffusion Process or Ion Implantation Process. [5] The diffusion process consists of introducing the dopant impurities to the Silicon substrate. [6] “The technique involved the exposure of the semiconductor slice to a vapor, containing the dopant of sufficient concentration, in a carrier gas to ensure the controlled dopant concentration at the semiconductor surface and at sufficiently high temperature to create diffusion rates that would provide precise control of the dopant penetration depth in the semiconductor.”[3] Diffusion can also be understood as migration of an atom or molecule from an area of high concentration to an area of low concentration. [5] It occurs through two steps – Predeposition and Drive-In. [5] The diffusion equation giving the relation between depth and concentration of dopants is as follows: [6] where; N(x,t): (1/cm3) is the impurity concentration at a diffusion time ‘t’ and certain depth ‘x’ D: (cm2/sec) diffusion coefficient of a given impurity at a given temperature. Predeposition Diffusion Process By predeposition, the dopant impurities can be made to penetrate the substrate to a desired depth and thus the concentration of dopants can be ensured by this process. [6] The solution of the diffusion equation by the aid of boundary conditions is as follows: [6] By putting the appropriate values in this equation and solving for dopant N-type i.e. Boron the predeposition diffusion conditions can be determined i.e. the depth of diffusion, the temperature, the time etc. [6] The Borosilicagel is taken as the source of Boron (dopant) and the atmosphere is that of 80% N2 and 20% O2. [6] The substrate is smeared with Borosilica gel and heated at 110 °C for 1 minute in air. [6] The deposited Boron is diffused at 1100 °C for 2h 49 min and then again re-oxidized at the same temperature for half an hour. [6] For the diffusion of emitter and collector the photolithography using mask #2 is done followed by removal of SiO2 and Photoresist. [6] It is then subjected to Phophorosilica gel and baked at 110 °C for a minute. The deposited Phosphorous is diffused at 1100 °C for an hour. [6] Drive-In Diffusion Process By the process of Drive-In the dopant impurity atoms are thermally ‘driven in’ the substrate to the specified depth and thus, the concentration of the dopant as well as the penetration depth can be controlled. [5-6] The solution of the diffusion equation by the aid of boundary conditions is as follows: [6] Again by the aid of suitable boundary conditions, the drive-in diffusion conditions and values of parameters can be determined. [6] The wafer is re-oxidized at 1100 °C for 30 min followed by photolithography using mask #3. [6] The SiO2 formed is removed by etching. [6] Ion-implantation Process In this process, the dopant impurities are ionized by putting them in an electric field to accelerate them and impinging them in the substrate. [6] On colliding with the substrate, the dopant penetrates to various depths depending on its acceleration. [6] Thus, this process is harmful to the planar surface of the substrate. [6] The wafer is annealed to restore it from the damage and to further embed the dopant impurity atoms in the substrate. [6] However, the process of ion implantation is advantageous in the way that it provides control over the depth and concentration of the dopant, excellently reproductible and is a low temperature process hence energy-efficient. [6] However, it is not an economical process. [6] METALLIZATION The active regions impregnated with dopant impurities along with the substrate cannot conduct electricity and has to be provided metal contacts. [6] This is precisely the reason for the step of Metallization in the fabrication process of BJTs. The metal contact which is provided is of Aluminum which has the valency +3. [6] However the usage of Nickel, Chromium, Gold, Copper, Silver, Titanium, Tungsten and Platinum is also common. [5] The popular methods of Physical Vapor Deposition (PVD) of metals are filament evaporation, electron-beam evaporation and sputtering. [5] The wafers are kept in the evaporation chamber at vaccuum where vapors of Aluminium are made to condense on the substrate surface. [6] The process of vaporization is brought about by heating Aluminum way above its melting temperature by resistance heating, rf heating or with a focused electron beam. [5] After sufficient time of exposure the wafers are taken out and immersed in acetone for ‘lift-off’ i.e. removal of excess Aluminum. [5] The wafers are shaken in an ultra-sonic vibrator after immersion in acetone. [5] Figure 4: Thermal Evaporator [5] ALLOYING PROCESS The alloying process is the final step in the fabrication process of BJTs. It consists of the following steps: i) After the successful metallization of the wafers, they are dried in a dryer using a nitrogen gun.[6] ii) The sample is loaded in the furnace and N2 gas is once again flown through the system for 2 min. Light the burner at the exhaust tube of the reactor. [6] iii) Turn on the furnace and begin monitoring the temperature. At a temperature of 350 °C change from ambient to Nitrogen/Hydrogen after ensuring that the gas starts to burn at the exhaust of the reactor tube within 2 min. [6] iv) At a temperature of 450 °C, begin alloy timing for 30 min. [6] v) When the alloying finishes, cool the furnace by flowing H2 in it until the temperature decreases to 350 °C. Change from ambient to Nitrogen and put off the burner. [6] vi) When the samples cool down to a temperature of 80 °C, they can be removed from the furnace after shutting off N2. [6] CONCLUSION After the alloying of the wafers takes place they are tested for performance. [4] The various tests that they undergo for physical characterization especially resistivity and doping concentrations are as follows: 1. Four-Point Probe Measurement 2. Hall Effect Measurement 3. SEM [4] The process of fabrication of Bipolar Junction Transistors is very sophisticated right from the start. The process of cleaning the wafers is a very detailed procedure and needs to be done effectively as impurities in any form will impede the current flow in the circuitry of the transistor and alter the results. ‘Wet’ Thermal Oxidation ensues cleaning to grow the required SiO2 layer on the Silicon substrate. The processes of Lithography, Etching of SiO2, Diffusion and Re-oxidation are performed in series till the active regions are not formed. Once the active regions are formed, they are ‘metallized’ by condensing the Aluminum vapor on them and subsequently alloyed. If the procedures are not properly executed, it may lead to failure in performance of the Bipolar Junction Transistor. REFERENCES [1] J. Nielsen, "Physical Fabrication of Transistors, from Point Contact to Planar Epitaxial" 22nd June 2005, http://www.cjseymour.plus.com/elec/basicfab/fab.htm [November 12th, 2011] [2] “RCA Clean.” Internet: http://www.ece.gatech.edu/research/labs/vc/processes/rcaClean.html [November 12th, 2011] [3] Howard R. Huff. “From The Lab to The Fab: Transistors to Integrated Circuits.” in ULSI Process Integration III, ECS PV 2003-06, 15-67 (2003). [4] Osama S Hammad et. al. “Thin Film Silicon-On-Insulator of Bipolar Junction Transistor: Process Fabrication and characterization Technology.” in International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1037-1046 [5] M. Z. Kabir, “Basics of Micro-fabrication,” class notes for ELEC 421/6221, Department of Electrical and Computer Engineering, Concordia University at Quebec, Fall 2011. [6] http://users.encs.concordia.ca/~shailesh/421labmanual.docx [7] http://people.seas.harvard.edu/~jones/es154/lectures/lecture_3/darmstadt/img021.jpg Read More