The Different Modes of Fabrication in CMOS - Essay Example

The History and Development of VLSI CMOS Technology The focus is mostly on the improvements that have occurred in CMOS technology. We explore the different fabrication methods that are used to bring this into a reality. Some of these methods are the SOI-wafer, p-wafer and n-wafer. These methods have their disadvantages and advantages making their use interchangeable according to the end product required. At the end, the paper tries to show how CMOS is getting to look as if it is a like an irreplaceable technology in the near future due to its many uses. Introduction Every day in the word transistors sizes and costs are decreasing while as their speed is increasing. The formation of MOS takes place by superimposing several layers of insulating, conducting and transistor forming materials. The CMOS technology provides two types of transistors namely the n-type transistor and the p-type transistor. Motivation The rapidity with which hardware technology is changing motivated writing of the paper. The main aspect was the reason that the hardware prices are getting cheaper while its quality is improving. History of CMOS The CMOS were invented in 1963 by Frank Wanlass. This technology has been used in every electronically digitally integrated circuit in the modern world. This has been made possible by their operating speed also reduction of size in every subsequent production of CMOS (Thes, 2008). The development in CMOS technology tends to rely on Moore’s law, which stated that, “an approximate 30% reduction in linear dimension and introduction of products with the new technology 2 years after the previous” (Sadan & Current, 2002). Figure 1: The three types of CMOS processing n-well, p-well and twin-well (Baker & Jacob, 2010). SOI (Silicon on Insulator) well fabricator on CMOS It was used in selected discrete and integrated circuits in 1960s. It was developed to be used for space exploration making it used in early satellites and space exploration systems (Colinge, 2010). These devices were fabricated with SOS (silicon on sapphire), but recently they are fabricated with SIMOX (separation by Implanted Oxygen). In recent world, SOI fabricators continue to be researched on due to their use in fabrication of the CMOS’s ICs (Marshall and Natarajan, 2002). Industry players believed by 2006-2008 there would be a huge shift to the fully depleted SOI CMOS would occur. During 2010, it was believed that 10% of the transistors would have been using this technology (Baker & Jacob, 2008). Modern usage of SOI wafer 1. IBM is using it in the high-end RS64-IV “Istar” PowerPC-AS microprocessor in 2000. 2. The making of AMD microprocessor. 3. Used in play station 3 and Wii. 4. Making of Intel processors. 5. Used in silicon photonic. Advantages of SOI 1. They were resistant to ionization by radiation which would have taken place due to the solar wind radiation in space. 2. It was also preferred due to the robust voltage isolation of IC. 3. Due to its ability to offer perfect transistor count which has led to lower leakage in transistors. This characteristic has led to continue use of SOI even in the modern world. 4. It is also known for faster performance and lower power consumption due to its reduced parasitic drain capacitance. 5. It ensures higher transistor count which ensures tighter transistor packing in devices. This ensure in reducing the size of devices. 6. It is seen to be less complex making it a choice by many to use. 7. The buried oxide plays a role within by offering thermal insulation in SOI. This insulation has an effect of elevating temperature within the SOI device which modifies the output of the device. 8. There is complete avoidance of the latch up problem. Disadvantages 1. The absence of substrate diodes complicates the protection of input and outputs against the ESD pulses. 2. The SOI technology is believed to be expensive making it not to be widely used in the modern world. This is brought forward by the need of single crystal sapphires. 3. There is a predicament with this technology in that input and output structures has to be larger. Twin_Well CMOS This is a technology that provides for separate optimization of the nMOS and the pMOS transistors. After the implementation, it allows for threshold voltage, body effect and channel trans-conductance of both types of transistors to be tuned independently. The well region is formed by n+ and p+ substrate (Veendrick & Harry, 2008). A diagram showing the twin well cmos where two p-wafers and the n-well are used (Veendrek & Harry, 2008). Advantages 1. Insulating substrates give high latch_up immunity. 2. The dopant concentration can be optimized to produce the desired device characteristic because of its ability to have two independent doping steps. 3. It is able to avoid the problem of unbalanced drain parasitic Disadvantages 1. It is expensive 2. It has extra processing steps 3. It does not offer higher integration density as the SOI fabrication N-WELL It is formed with diffusion or ion implantation. It starts with a moderately doped p_type silicon substrate. An entire oxide layer is grown on the entire surface. A lithographic mask defines the n-well region. Through this window, phosphorous are implanted in the oxide. This leads to the formation of n-well. In the modern day, some devices after being fabricated with the N-well they are implanted with boron over the substrate. These devices have a threshold voltage comprising between 1.1 and 1.2V and below a ground slope of 75-80 mv/decades (Chang & Sze, 1996). Usage It can be used as a resistor – this is enabled by keeping the voltage on either sides of the resistor large enough to keep the well from forward biasing. Disadvantages The boron that is implanted after the N-well is adequate to concurrently form an anti punch-through diffusion. Advantages 1. It is fast than the p-well. 2. It provides optimum devices characteristics. 3. It provides density in its ability to occupy small spaces. 4. Implants are used to control the threshold voltages of the transistors. P_WELL fabrication This fabrication of CMOS was developed in 1980s. Most transistors use wells for both the n-channel and p-channel. Its formation starts by having a moderately doped n-type substrate. The P-type is created for the n-channel devices and builds the p-channel transistor in the native n-substrate. The field oxide is etched away to allow for the deep diffusion of the fabricator (Mead, Carrer & Conway, 1980). Usage 1. Used in formation of logic elements due to its ability to provide speed and density. 2. They are used to make super junctions 3. Used in making of the twin-well together with the n-well. 4. It is used in formation of pMOs transistor in the epitaxial layer. 5. It is mostly used to make pull up devices. Disadvantages 1. There is a need of larger spacing between the n- and p- transistors leading to development of larger chips, which are not good. 2. The higher voltage in P-well can cause latch problems in it. 3. It is slower in performance – this is brought about by the higher concentration, n transistor suffers from excessive source/drain to P-well capacitance. 4. The injected current in the substrate is collected by the P-well leading to the need of grounding it to minimize voltage loss. Conclusion The different modes of fabrication in CMOS have supported a lot of shrinking in it bringing with it advantages in terms of cost, speed and power. This technology is getting to a dead end because no improvement in silicon seems possible for cost reduction. This has led for the need to try and research on other technologies like the double-gated (DG)(Colinge, 1997). References Baker, R. Jacob (2008). CMOS: circuit design, layout, and simulation. Boston: Wiley-IEEE. Baker, R., Jacob (2010). CMOS: Circuit Design, Layout, and Simulation (3rd edition). Boston: Wiley-IEEE. Chang, C. and Sze, M. (1996). ULSI technology. New York: McGraw-Hill. Colinge, J. (1997). Silicon-On-Insulator Technology: Materials to VLSI, Second Edition. Rijnald: Kluwer Academic Publishers. Marshall, A. and Natarajan, S. (2002). SOI Design: Analog, Memory, and Digital Techniques. Rijnald: Kluwer Academic Publishers. Mead, A. and Conway, Lynn. (1980). Introduction to VLSI systems. Boston: Addison- Wesley. Sadana, D. and Current, M. (2000). Fabrication of Silicon-On-Insulator (SOI) Wafers Using Ion Implantation. Boston: Addison-Wesley. Theis, T. (2000). The Future of Interconnection Technology. New York: IBM J. Res. Develop. Veendrick, Harry J. (2008). Nanometer CMOS ICs, from Basics to ASICs. New York, NY: Springer. Read More