Design Project and Application of Plan, Do, Check and Act Concept for Quality Improvement - Case Study Example

Application Of Quality Management by Ravi Prakash Academia Research Presented Academic Writing. Freelance Bhusawal, Maharshtra, India. 15 Mar 2009. "This paper presents a case study of a semiconductor IC design project & application of PDCA (Plan, Do, Check & Act) concept for quality improvement, implementation process, monitoring and evaluating the quality improvement, series applying actions to the outcome for necessary improvement found in previous every cycle as aim in next cycle. It presents an example of continuous improvement of process in an engineering organization. It's a trial of writer to include both technical management as well non-technical management processes to make this paper handy for practitioners of PDCA in all kind of industries. It also demonstrates both conceptual & analytical ways to solve various flow & process related problems in a step by step manner." Contents: Page. Introduction Of Organization..... 05-05 Background Of Department Under Study...... 05-05 Project Overview.. . 05-05 Project Technical Challenge... 06-06 Project Management Challenge ... 06-06 Condition Of Department in July 2007 .... . 06-08 - Technical Team Distribution .... 07-08 Present Challenge For Design Library Manager. 08-08 Cycle 1 Of PDCA ... 08-10 - 1.1 General Quality Improvement Planning (P-Plan) 08-08 - 1.2 General Process Implementation Of Cycle 1 .. 08-10 1.2.1 Quality Improvement Plan (P-Plan) ...... 08-09 1.2.2 Process Implementation (D-Do) 09-09 1.2.3 Monitoring & Evaluation (C-Check) . 09-09 1.2.4 Apply Actions Of Outcome (A-Act) . 10-10 Cycle 2 Of PDCA ... 10-12 - 2.1 General Quality Improvement Planning (P-Plan) 10-10 - 2.2 General Process Implementation Of Cycle 2 .. 10-12 2.2.1 Quality Improvement Plan (P-Plan) ...... 10-11 2.2.2 Process Implementation (D-Do) 11-11 2.2.3 Monitoring & Evaluation (C-Check) . 11-12 2.2.4 Apply Actions Of Outcome (A-Act) . 12-12 Cycle 3 Of PDCA ... 12-15 - 3.1 General Quality Improvement Planning (P-Plan) 12-13 - 3.2 General Process Implementation Of Cycle 3 .. 13-15 3.2.1 Quality Improvement Plan (P-Plan) ...... 13-13 3.2.2 Process Implementation (D-Do) 13-14 3.2.3 Monitoring & Evaluation (C-Check) . 14-14 3.2.4 Apply Actions Of Outcome (A-Act) . 15-15 Overall Process Performance (P) Evaluation ... 15-16 Suggestion To Improve PDCA . 16-16 Conclusion 17-17 Glossary 18-19 References . 20-20 Appendix - 1 . 21-23 - TOWS Matrix For Cycle 1 .. 21-21 - TOWS Matrix For Cycle 2 .. 22-22 - TOWS Matrix For Cycle 3 .. 23-23 Appendix - 2 . 24-25 - 2.1 Standard Cell Library Design Process Flow .. 24-24 - 2.2 Standard Cell Library Characterization Process Flow .. 25-25 Introduction of Organization: Organization: Conexant Systems Inc. (NASDAQ: CNXT) - INDIA Design Center (IDC - Hyderabad)). CEO: Mr. Steve Sanghi. (Former) (During project in this case study). Industry Type: Semiconductor IC Design (Product Based MNC). - Fabless (Uses TSMC, Jazz & UMC facilities for fabrication of their IC products.) Company's Products: Audio (Speakers-on-a-Chip, PC HD-Audio, PC HD-Audio Modem Combo), Video (MPEG Encoders/Codecs, Video Decoders, Demodulators, Surveillance / Security, Imaging Solutions), Fax Modems (Fax and MFP System Solutions, Digital Photo Frames, Dial-Up Access Modems), PC Dial-Up Modems (Embedded Dial-Up Modems, Broadband Access - Client Side), ADSL Solutions (VDSL Solutions, SHDSL Solutions, Embedded Communications Software, Broadband Access - Central Office), ADSL Solutions (VDSL Solutions, SHDSL Solutions), Passive Optical Networks (GPON & BPON). Company URL: http://conexant.com Quality Management Standards: According to ISO 9001:2000, Auditor: DNV Certified. Environmental Standards: DNV EMS Certified. Background of Department in Organization (For Present Case Study): Department Chosen: Foundation IP BU (Standard Cell IP Development) Business Unit Head & Standard Cell Library Manager: Mr. Kedar Kulkarni. Project Date: July, 2007. Project Overview: Re-establishment of a CMOS (Complimentary Metal Oxide Semiconductor) IC design library team for improvement in layout views for compliance with new 65nm Design Rules (Physical / Layout Design Rules) & DFM (Design For Manufacturability) rules to cope up with the demands of area reduction challenges & compliance of the design with manufacturing constraints of 65nm feature size & high yield assurance, targeted to TSMC fab for manufacturing. Project Technical Challenge: Technology migration from 11 track to 9 track standard height of each cell in 650 TSMC GP standard cell library. Fixing physical verifications including DRC (Design Rule Check) violations, LVS (Layout v/s Schematic) violations, DFM (Design For Manufacturability) violations, Timing Sign off - Static & Dynamic Timing Failures, to qualify the design library for new area constrained chip synthesis & integration. The old library was full of DRC, LVS & DFM violations because of which the results of post silicon tests on last released test chip were failing the reliability constraints during failure analysis those were very critical to be cured sincerely before the actual product launches in the market, else, may result in run time failures & degradation of the market value of Conexant's IC products. Project Management Challenge: A Separate BU (Business Unit) called Foundation IP was working on providing library design solutions to Conexant's internal customers (Physical design & Sign off teams). Challenge was to establish a team of competent technical ASIC / VLSI design engineers who could be able to complete this project in 30 days (Actual time required to renew a library of 650 cells in approximately 60 days to 75 days through minimum 8 skilled engineers in relevant domain in various stages, if consider an economic team & every single is considered to be an individual contributor or expert in the particular phase of design flow) as the library has to be made available to the chip integration or physical design & sign off / pre-silicon validation teams that has to be done in 60 days before it is taped out to the foundry. The time was very short & an impractical deadline has to be met. Condition of the Standard Cell Library Team in July, 2007: Technical Team Size: 5 Newly Hired Senior Design Engineers (E1/E2 Grade). Library Managers Role: Responsible for collection of complaints & bugs in design library from all internal customers of Conexant Systems Inc. on daily basis by meeting up with them through video conference for geographically distributed teams & by phone, meeting with local office on physical presence in discussion with them or in their cabins. Documentation of bugs & development of specifications for library design team for relevant requirements or corrections. Application of engineering experience in solving designers all technical & non-technical issues with on-going projects, training design engineers in technical aspects of solving design problems & making aware of latest trends in the industry. Development or modification of design flows, project planning (time, amount of work, design related technical plans to approach the problems & solving them ...etc), implementation of plans, checking & evaluation of performance of project execution process. Technical Design Team Distribution: 1. One Engineer for Front-end Design (Digital wire load model analysis & topology selection, CMOS circuit design) & Front-End Verification (Spice simulation & analysis). 2. Two Engineers for Physical Design (Layout Generation, Technology Migration, Layout View Modifications) & Physical Verification for design sign off (DRC/LVS/DFM - EMC (Electro migration Check & Fixing for prevention from burn outs, heating due to EM in various metal lines & cross talk/noise interference between them), LUP (Latch-up Check & Fixing for prevention from chip burnouts due to low resistance paths or parasitic latch up unwanted circuits formed due to parasitic components (parasitic capacitances & resistance) substrate) that may result in power & ground line shorts, Boundary Checks (Half-DRC (for inter cell design rule compliance) / Abutment Checks & Fixing for prevention of over etching/uncut during fabrication by all possible cell orientations in horizontal abutment), Charge density checks & fixing for uniform charge distribution & filling for minimization of micro fractures.). 3. One Engineer for Layout Parasitic Extraction (LPE) & Post Layout simulation on extracted net-lists for analyzing the EM (Electro migration), Noise interference & Performing delay characterization. Reporting back to physical design engineers with characterization report for checking & corrections in physical design. 4. One Engineer for layout views, schematic views, HDL model generation & their validation for functional, noise & timing compliance with the specifications. Final release of all views to test chip teams (internal customers) working on RTL Synthesis, Integration & Chip sign off/Pre-silicon validation teams (STA (Static Timing Analysis), DFT (Design For Testability), Power & Noise Characterization on chip level). Present challenge in front of library manager & design team: In-sufficient number of engineers for execution of project in 30 days, it will take not less than 75 days to complete the project with present work force of five engineers. The tasks were already over loaded & engineers are already highly exploited & increasing it more may result in dis integration of team or loosing the team itself, because of continuous labor law violations in working hour limitations & severely challenging human capability, dominating/affecting their personal lives & time, may result in indulgence of company in legal issues, if some body bothered it & reacted in against. Cycle 1 of PDCA: 1.1 General Quality Improvement Planning of Cycle 1 What is manager was trying to accomplish To complete the project within 30 days. How will he know that a change is an improvement He prepared a TOWS matrix to update the projects proceeds and if weaknesses & threats start reducing that would be an indicator of an improvement. What changes can he make that will result in improvement Transparent communication with stakeholders to know their minds & opinions & to proceed with the most relevant need. 1.2 General Process Implementation using PDCA of Cycle 1 1.2.1 Quality Improvement Planning (P-Plan): To make own flow for Standard Cell Library Design Cycle. (See Appendix - 2). To hire five more experienced engineers, to relax the present load & distribution of work load will reduce individual pressure. 1.2.2 Process Implementation (D-Do): Manager documented the roles & responsibility details of desired skills to be searched to HR. After research on internet & through her corporate network, she found it very difficult to find engineers with the characteristic sets demanded and even if managed to find one or two, they were too much expensive to hire for their present project budget and wasn't sure, if they were the right peoples for this job as the combination of job roles involves many skills & competency that individually cost very high in the job market & the results of search for peoples with multiple skill set was depressing. The time constraint was one of the main factor that compelled her to discuss with library manager back on this issue. Manager decided to go with present work force & to prepare a TOWS matrix (See Appendix - 1, Cycle -1) in order to perform an internal analysis of library team to determine the strengths, weaknesses, threats & opportunities for evaluation of present team situation & to find clues for beating the weaknesses & threats efficiently utilizing all the possible opportunities & strengths already available in team. He prepared the matrix & discussed with design team for its follow-up & to ensure the compliance of work practices with it. Team tied up their belts to face the impractical project with positive hope & started working on projects in relevant phases with good collaboration & autonomously as well. 1.2.3 Monitoring & Evaluation (C-Check): After a week time the manager found the same thing that he was scared of, the deadline could not be met with this pace & workforce, the team needed to work on 24/7 hours in order to meet the deadline that was impossible. Manager discussed with design team, but, physical design engineers presented their views on withdrawal or they may leave the service. On seeing the team members loosing hopes, the front-end design engineer also, expressed the similar views. After thinking on engineers points of dis satisfaction, manager decided to re-plan the project a fresh. TOWS Matrix of cycle 1 see Appendix - 1, Cycle -1. 1.2.4 Applying actions to the outcome for necessary improvement (A-Act): Manager discussed with design team again & in meeting they came to a conclusion to hire some stakeholders that would be cost efficient & also, distribute the individual load. And installation of some technique that doesn't require much expensive manual works & team to hire. Engineers & Manager Developed their Design process flow. (See Appendix - 2) Cycle 2 Of PDCA: 2.1 General Quality Improvement Planning of Cycle 2 What is manager was trying to accomplish To install cost efficient techniques to distribute the individual load on stakeholders & complete the project within 30 days with a wise systematic approach. How will he know that a change is an improvement In his TOWS matrix if weaknesses & threats starts reducing or become nil will indicate an improvement. What changes can he make that will result in improvement To discuss with stakeholders to know their urgent requirements to complete the project & solving every single problem in a step by step manner & reducing the complexity in the project handling. 2.2 General Process Implementation using PDCA of Cycle 2 2.2.1 Quality Improvement Planning (P-Plan): Manager planned to discuss with all stakeholders before taking any decision, so, he arranged a meeting with design team to plan a specific skill hiring exactly relevant to tackle present challenges & to reduce or distribute the manual drawing or modification of layouts. Design engineers presented their views about facing difficulties in manual mechanical layout works, it must be done through mechanical trade diploma technician & could also be able to run at least DRC & LVS verifications of every layout & to fix common errors before sending it to engineers & also help engineers to concentrate on critical problems of reliability & yield loss. Secondly, a design automation engineer has to be hired with ample skills in data automation works to help them in design flow integration (design tools integration & support) & abutment view generation that requires an expert level practical skills in Perl, UNIX/bash/shell & SKILL scripting languages. 2.2.2 Process Implementation (D-Do): Manager agreed with engineers & prepared the requirements for HR to search these competencies. He increased the budget to accommodate the expectations of deserving candidates & to attract the relevant talent as soon as possible, requirement specifications given to HR consist of confirmed & recognized skills required as per design engineers & some marketing advertisement to attract the candidates like job security assurance, 30% - 50% hike from their present salaries & human friendly cheerful work atmosphere...etc. Mentioned the need of candidates who can join in a short notice period of 1 week at the most & supported this with compensation for notice due fulfillment to join early & relocation/ accommodation expenses incurred for first month. HR found it easy to go with these requirements as the skills were now balanced with good benefits & could become a reason to pull out good candidates. In 3 days HR found a skilled layout technician of about 5 yrs IC layout drawing experience & skills matching with the displayed requirements on various job portals & networks, within 2 more days she was able to get a amply skilled automation engineer. And informed library manager about her findings & sent the profiles of candidates to design engineers on approval from library manager & if found suitable than proceed for technical rounds, both candidates were found to be suitable for there works, except few doubts about layout technician, they called them for face to face interviews & tested for some situational tasks for both in their relevant skills, their aptitude to think of innovatively & speed of performance test, in 2 days of technical rounds they found them suitable, with a set of weaknesses & difficulties in understanding & doing their works, they found it feasible to hire them as their strength & experience in the concerned area were decent & technically sound. 2.2.3 Monitoring & Evaluation (C-Check): The team was now equipped with required competencies to work on the project. Library manager started noting down the changes in his TOWS matrix (See Appendix - 1, Cycle 2), after one week of work he found the team to be double productive & can think of meeting the deadline of 30 days that is almost half of the minimum time period required to do that project with previous resources, was now compensated with double productivity. And design engineers could be able to find time to concentrate on reliability & DFM issues, physical design engineers could do the simulation for timing delays, power on cells to come up with design constraints for technician to follow while modification of layout views, layout technician was an expert, so, needed a slight supervision to complete his tasks timely & enthusiastic about coping up with the situation as salary & benefits were good. Hiring of design automation engineer solved the problem of design integration & released them from the complexities of large files to handle & data processing, it did a great help in automation of most of the manual works through scripting & load on the design engineers was distributed without hiring more experienced VLSI design engineers, that was a good deal for project budget as well as technical work execution. 2.2.4 Applying actions to the outcome for necessary improvement (A-Act): Now their was a critical problem in DFM & reliability issue to handle, as it requires deep understanding of PDK (Process Design Kit) for power grid simulation, design rule development & their constraints. Design team had to solve these issues to ensure DFM compliance. Now this systematic approach had narrowed down the number of challenges through step by step planning & solving one by one, reduced the complexity of the problem. Cycle 3 Of PDCA: 3.1 General Quality Improvement Planning of Cycle 3 What is manager was trying to accomplish To collect all necessary resources indicated by stakeholders, without incurring extra expenses or wastes. How will he know that a change is an improvement In his TOWS matrix if weaknesses & threats starts reducing or become nil will indicate an improvement. What changes can he make that will result in improvement To discuss with stakeholders to know their urgent requirements to complete the project & solving every single problem in a step by step manner & reducing the complexity in the project handling. Completion of project utilizing collected resources on or before deadline. 3.2 General Process Implementation using PDCA of Cycle 3 3.2.1 Quality Improvement Planning (P-Plan): Manager followed the same routine as it seemed to be successful, he arranged a meeting with design engineers to let them present their ideas about how to proceed & tackle with present issues, they presented their views on their difficulties in doing the Power Grid Analysis, SI (Signal Integrity Analysis) and issues with old DFM rules those were to be revised & also the old DRC rules to be made compliant with 65nm technology rules. So, they came to a conclusion to contact & discussing it with TSMC foundry to ask for upgrading & suggesting solutions or techniques to renew design rule decks & manufacturing challenges in UDSM (Ultra Deep Sub Micron) technologies i.e., below 90nm feature size. To solve the problem of SI & power grid, it was feasible to employ modern tools like Voltage Storm (of Synopsys Inc.) or Celtic NDS (of Cadence Design Systems) that could drastically reduce the analysis time & complexities of the concerned problems above & help them to meet the deadlines. Manager decided to contact TSMC for assistance in DRC & DFM rule deck updating & provision of techniques to meet those challenges. Also, contacted Cadence Design System & Synopsys Inc. for the pricing catalogue of various licenses of EDA tools for SI analysis & Power grid simulation. 3.2.2 Process Implementation (D-Do): Manager got the response from customer service personnel of respective EDA vendors about his queries on license costs & catalogue with detailed tariff. He wanted to let the design engineers to evaluate these tools first, before employing them & also, asked for training on selected tools & further clarifications on different types of licenses offered by them. Up on presentation on those tools by respective companies' application engineers, they found both tools to be relevant & of good use for them, they discussed on types of licenses available & found the pricings of multi-user or batch licenses to be suitable for their budget. They took the decision to employ both of those tools, installation completed within 2 days with assistance of application engineers of respective EDA vendors. Upon talking to TSMC foundry engineers, they found their design rules were outdated & will definitely result in a disaster, if used for present project. So, design engineers asked them for new set of design rule manuals for DRC & DFM. They now had an automation engineer recently hired, who could be of great use in developing rule decks for DRC & DFM according to the rule manual they got from TSMC foundry. Automation engineer started working on modification of existing DRC & DFM rule decks as well as PEX (Parasitic Extraction net-list & report generation) to be ran on physical verification tool they had been using i.e., mentor graphics - Calibre tool, to update with new constraints as per manual given to him. 3.2.3 Monitoring & Evaluation (C-Check): Upon all above changes, design engineers performed the power grid analysis, SI analysis, static & dynamic timing analysis, ensured the design rules & DFM rules were successfully implemented in physical verification system. Ensured the layout development tasks were going on, as per the constraint sets given to the technician upon subsequent delivery of layouts & their analysis on timely basis. Started finding time to discuss with characterization engineer to help in delay extraction & simulations, requirements of validation & release engineer, who was performing PVT (Process Voltage Temperature) Corner analysis on every cell analyzed by design engineers on constant basis that helped in further reduction of time in collaborative works. Library manager updated his TOWS matrix (See Appendix - 1, Cycle - 3) with present situation of the internal environment & project execution, he found all the weaknesses are been recovered & threats are suppressed. 3.2.4 Applying actions to the outcome for necessary improvement (A-Act): On 27th day all the cells were completed according to library manager's estimation of project execution plan. Validation engineer generated the final cell views (Schematic or circuit views, layout views & symbol views) & models (HDL & liberty models), and performed validation of views & models. All HDL models were found accurate on functional & as well as timing perspective, liberty model that included all matrices of delays v/s loads of each cell, noise susceptibility, thresholds of capacitances (input pin & output load capacitances), voltages & temperatures to ensure their reliability in adverse conditions of cold & heating atmospheres. He found few cells not meeting the thresholds of temperature & voltages, that was sent back to design engineers, they analyzed the extracted net lists of respective cell layout to find the causes in parasitic capacitances & resistances, did few changes up simulation & given it to layout technician for modification in those cell layouts. Again, did the modification & sent to design engineers, they found it successful upon post layout simulations & sent them back to validation engineer for validation. Every thing held according to plan & validation completed successfully. On 30th day, Validation & Release engineer released the library views (abstract views of - circuit schematics, symbols, GDS of layout, timing views, power views, HDL & liberty models and library IP documentations) for internal customers to proceed with their chip integration & sign off tasks. The mission accomplished on time. Overall Process Performance (P) Evaluation: TOWS Threats (T) 10 (-) Opportunities (O) 10 (+) Weakness (W) 10 (-) Strengths (S) 10 (+) Performance (P) -20 to +20 Cycle - 1 4 3 6 2 -5 Cycle - 2 2 5 3 5 +5 Cycle - 3 0 8 0 8 +16 Formula: P = [(S+O) - (T+W)] P (Cycle 1) = -5, P (Cycle 2) = +5, P (Cycle 3) = +16. Consideration: 0 as Minimum Good Performance, +20 as Maximum Good Performance. 0 as the Minimum Bad Performance & -20 as Maximum Bad Performance. E.g.: If the P is negative it shows threats & weaknesses are more than Strengths & opportunities, & P is positive than vice-versa. Present Statistics: %P (Cycle 1) = Under Performance of 25 % (Out of 20 Negative) %P (Cycle 2) = Positive Performance of 25% (Out of 20 Positive) %P (Cycle 3) = Positive Performance of 80%. (Out of 20 Positive) Increment in performance from Cycle 1 Cycle 2 Cycle 3: Cycle 1 Cycle 2 Performance Increment = +10 (+50 %) (Out of 20 Max. Positive) Cycle 2 Cycle 3 Performance Increment = +11 (+55%) (Out of 20 Max. Positive) Cycle 1 Cycle 3 Performance Increment = +21 (+52.5%) (Out of 40 Max. |-20| + |+20|.) Suggestions to improve PDCA 1. Every Phase of PDCA i.e., Plan, Do, Check & Act can be associated with options to select standard analytical techniques to perform particular stage of cycle. 2. As did in this case study the overall performance evaluation option can also be included in this concept to increase the depth, widths & scope of PDCA. Conclusion: The conceptual & analytical techniques can make PDCA more useful for all kind of process improvements. The case study identifies the number of cycles to apply PDCA on Standard Cell Library development process improvement. The monitoring of the process improvement has been done through industry standard tool called TOWS in all three cycles (See Appendix - 1). The evaluation of the process performance is performed with a customized method of tables & analytical charts using simple custom derived formula (See "Overall Performance (P) Evaluation" Section above). And the detail technical design flows are developed especially for this case study (See Appendix - 2). After all results of analysis, it has been found that PDCA has given a prime contribution in resolving the complexities of the problem, through a step by step procedure according to its concept. The improvement can be analytically noticed through the bar graph shown in the section "Overall Performance (P) Evaluation" above. The case study presents the successful application of PDCA concept. Glossary ASIC: Application Specific Integrated Circuits. BU: Business Unit. CEO: Chief Executive Officer. CMOS: Complimentary Metal Oxide Semiconductor. DFM: Design For Manufacturability. (A design for compliance with the foundry etching resolutions & manufacturing process to save yield.) DRC: Design Rule Check. (Layout Design Rules.) EDA: Electronics Design Automation. EMC: Electro Migration Check. (A property of metal depending on density of charges or flowing through the metal line, resulting in loosening of ions from the metal surface while flow of current may result in open circuit or accumulation of ions on metal joints that may result in short with adjacent metals of same hierarchy.) Fab: Fabrication Unit. IC: Integrated Circuits. LPE: Layout Parasitic Extraction. (Same as PEX) LUP: Latch Up. (A failure of circuit due to development of low resistance paths between power & ground lines through parasitic latch up structures formed in the substrate by accidental combination of N & P type substrate, resulting in formation of transistor type structures connected in a loop fashion offering low resistance path between power & ground lines.) LVS: Layout v/s Schematic Check. (To check the connectivity of layout, if it is exactly same as of circuit connectivity or not.) PEX: Parasitic Extraction. (Extraction of Parasitic/Unwanted Capacitances & Resistances in the silicon substrate & between the metal lines) PVT: Process, Voltage & Temperature. RTL: Register Transaction Level. (A representation of data flow from one component to another.) HR: Human Resource. SI: Signal Integrity. (The cross talk & a parasitic capacitance/coupling between laterally adjacent metal lines.) Spice: A net-list of circuit connectivity information. STA: Static Timing Analysis. (Non-transient simulation of delays to check various timing/frequency related violations.) TOWS: A standard framework for external & internal analysis of an organization that stands for Threat, Opportunities, Weakness, Strengths. TSMC: Taiwan Semiconductor Manufacturing Company. UDSM: Ultra Deep Sub Micron. (Feature Size of a transistor is less than or equal to 90nm) VLSI: Very Large Scale Integrated Circuits. References PDCA Concepts are used for quality improvement, no other direct references. For further reference of concepts & examples of application of PDCA, Please Refer: TOWS Matrix Concepts are used for monitoring the process during each cycle, with no direct citation on this case study. For more information, Please, Refer: "The TOWS Matrix" Weihrich. H, Professor of Management, University of San Francisco, n.d, [Internet], Date Accessed: 14 March 2009, Available At: Material for Company Information had been collected from: Conexant Systems Inc. Corporate Website, n.d, [Internet], Date Accessed: 14 March, 2009, Available At: All analysis & evaluations are done by writer on experience in the field concerned. Appendix - 1 Appendix - 2 2.1 This Design Flow describes the typical flow of processes made & followed by physical design engineers. 2.2 This Design Flow describes the typical design flow for characterization & post layout simulation, developed by physical design engineers for ensuring the quality of layouts & design. Read More