Amplification, Rectification and Applications in Motor Design - Essay Example

Amplification, Rectification and Applications in Motor Design of Affiliation] Table of Contents List of Figures Figure AC 6 Figure 2: AOG 7 Figure 3: AFR 7 Figure 4: LPF 8 Figure 5: AFR with Filter 9 Figure 6: RC 10 Figure 7: A & R with FR 10 Figure 8: AFC 11 Figure 9: FACO 11 Figure 10: SSD 13 Figure 11: SSD-BCD Decoder Circuit 15 Figure 12: Seven Segment Displays 16 Figure 13: EBSC 18 Figure 14: A-D Converter 18 Figure 15: FC 19 List of Tables Table 1: Table of Truth 12 Table 2: Output of the system 12 Table 3: TBC 17 Introduction This course work aims at designing of motor circuits, which are both digital circuits and analogue circuits that are used in various sectors to carry out varied tasks. The primary aim of this study is to analyze various characteristics of the motor, which include its speed, the amplification, and the display of various parameters. The study of this course can further be summarised as, optimizing the motor circuits both analogue and digital, designing the digital circuit parameters, circuits both the analogue and digital that are meant for the amplifiers, designing low-pass filters of the system, designing of the 7-segment display decoders of the system, and finally, simulating the various components of the whole system. Following the course guidelines when designing the system, it is advisable that all the current signals must be converted to milli ammeters that range from 2.5 mA to -2.5 mA. The required range of voltage signals for the system should range from a voltage of 3V to a voltage of 2V. After fulfilling the conversion recommendations of the system, suppress any noise that may be available in the system AC signal with frequencies exceeding 100 Hz. When all the parameters of concern have been validated, the conversion of the analogue circuit to digital circuit then follows while maintaining the A-D converter at 8-bit. Finally, relay the digital signal of the 8-bit to the 7-segment in order to get the display. System’s ADC clock is relayed by the converter. Analysis of requirements and work breakdown The circuit design of the motor is discussed with regard to its two components thus, systems analogue circuit and systems digital circuit. The functionality of the systems analogue circuit is based on signals that emanates from the low currents and are converted to signals of the voltage and finally the noise is filtered from the signals that originate from the alternating current of the system. Various components make up the analogue circuit thus, circuit rectifiers, circuit low-pass filters, and the circuit amplifiers. (Langevin & Riopel 2005).  System Circuit Rectifiers (SCR) Alternative Current Voltage (ACV) is converted to the signals of the DCV with the help of SCR. The low-pass filters of the system is the used to filter any noise present in the ACVS after the amplification and the amplifiers are finally used to amplify signals of lower magnitudes of current to the recommended ranges of the VS. The digital circuit components are classified into various categories thus, A-D converters of the system, synchronous counter that is 8-bit, SSD decoders, and BCD decoders. The D-A converters help to convert the ACS to the DCS. BCD-SSD converters of the system are useful in the display of system signals that are converted digitally on the 7-SUD (segment unit of display) (Langevin & Riopel 2005).  System Amplifiers (SA) SA’s are mechanisms of the system that help to achieve the recommended gain. Analogue Circuits (AC) are used to provide the (OV) of the range 3 V to 2 voltages and with ranges in (I) of 2.5 mA to (I) of -2.5 mA (Tao 2003).  x Rin=[Rf]/[A+1] x] Output voltage = [5.510-1 K-2.5m] Output voltage = [1.375100 V] Gain = Rf = [5.510-1 k] The open loop of bandwidth is fixed at 10 Hertz Fol is fixed at 10 Hz A is fixed at 104 Fcl = [1101]+ [104101] = 1 Mega Hertz. This is illustrated in the graph in the figure below Rin = [5.510-1 K ]/[104] = 1 Ω Figure 1: AC Figure 2: AOG Figure 3: AFR Component of Low Pass Filter (LPFC) LPF are meant for cutoff frequency that does not exceed 102 Hertz. The system component calculations and values include, Fc = [1]/ [(2π) (RC)] Resistance equals to 1100 Ω Capacitance equals to 1.5101 mF Fc equals to 102 Hertz It can be seen from the FFR that gain reduces by 3 dB after reaching a frequency of 102 hertz. Figure 4: LPF Figure 5: AFR with Filter System Rectifiers (SR) SR’s are components that help to convert ACS to DCS and while making use of the diodes. Capacitors are put into use in order to smoothen the DCS to achieve the required parameter ranges (Tao 2003).  Figure 6: RC Figure 7: A & R with FR Figure 8: AFC Figure 9: FACO DPC BCD-SSD Decoder Digit s p k q 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 F 1 0 1 0 E 1 0 1 1 D 1 1 0 0 C 1 1 0 1 B 1 1 1 0 A 1 1 1 1 Table 1: Table of Truth S R Q P O N M 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 Table 2: Output of the system Figure 10: SSD Using K Maps to derive the equations a=s, b= p, c=k, d=q S=kq’+pk+sq’+p’q’+s’p’k+sp’k’+s’pq [SOP] S’=[ k’+ q][ p’+ k’][ s’+ q][ p + q][ s + p + k’][ s’+ p + k][ s + p’+ q’][POS] R= s’ p’+ s’ k’ q’+ s’ k q + s k’ q + p’ q’+ s’ p’ k [SOP] R’=[ s + p][ s + k + q][ s + k’+ q’][ s’+ k + q’][ p + q][ s + p + k’] [POS] Q= s p’+ s’ p + s’ k’+ k’ q + s’ q [SOP] Q’=[s’+ p] s + p’] [s + k] [k + q’] [s + q’] [POS] P= s k’+ p k’ q + s p’ q + p k q’+ s’ p’ k + s’ p’ q’ [SOP] P’=[s’+ k] [ p’+ k + q’] [s’+ p + q’] [ p’+ k’+ q] [s + p + k’] [s + p + q] [POS] O= s p + k q’+ s k + p’ q’ [SOP] O’= [s’+ p’] [k’+ q] [s’+ k’] [p + q] [POS] N= k’ q’+ s p’+ s k + p q’+ k’ p k’ [SOP] N’=[ k + q +][ s’+ p][ s’+ k’][ p’+ q][ s + p’+ k + [POS] M= s p’+ k q’+ k p’+ s q + s’ k’ p [SOP] M’=[s’+ p] [k’+ q] [k’+ p] [s’+ q’] [s + k + p’] [POS] POS and the NAND gates make the circuit of the system. Common cathodes of the SSD help to save a NOTgate. Figure 11: SSD-BCD Decoder Circuit Figure 12: Seven Segment Displays 8-Bits Synchronous Counter SC is used in the system, which is different from the asynchronous counter given that it consists of flip-flops that are supplied by the clock pulses. One advantage of the SC is that they have the capability to build faster counters and with reduced synchronization interferences to system components. (Tao 2003).  Clock cycle Qa Qb Qc 0 0 0 0 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 1 1 8 0 0 0 Table 3: TBC Da equals to Qa ^ Enable Db equals to Qb ^ Qa .Enable Dc equals to Qc ^ Qb.Qa .Enable Dd equals to Qd ^ Qc.Qb.Qa .Enable This equation of the counter can be written as, Dn equals to Qn XOR (Qn-b . Qn-c . . Qb . Qa . Enable) Figure 13: EBSC Figure 14: A-D Converter Figure 15: FC References Langevin, A., & Riopel, D. 2005. Logistics systems design and optimization. New York, Springer. Tao, G. 2003. Adaptive control design and analysis. Hoboken, N.J., Wiley-Interscience.  Appendix KEY WORDS AC-amplifier circuit AOG-amplifier output gain AFR-amplifier frequency response LPFC-low-pass filter component FFR-filter frequency response LPF-low-pass filter SR-system rectifiers ACS-analogue circuit signals RC-rectifier circuit A & R-amplifier and rectifier AFC-analogue final circuit FACO-final analogue circuit output DPC-digital part of circuit SSD-seven segment display EBSC-eight bit synchronous counter FC-final circuit Read More