Comparative Characteristics of the Hybrid Networks on Chip and the Networks on Chip - Research Paper Example

Utilization of Hybrid Networks-on-Chip (HNOC) Network-on-Chip (NoC) was built upon interconnectwires, and they were expected to meet the stringent performance needs of the technology nodes. Conventional NoCs heavily relied on several packet-switched communications, whereby data packet needed to go through a series of routers with significant latency and power implications. However, in responding to this crisis related to interconnection, the Hybrid network-on-chip (WNoC) was envisioned as one of the most revolutionized approach. In this paper, it discusses how Hybrid network on chip is better than Network on Chip. Introduction Performances of a microprocessor have gone up exponentially in the last three-four decades. In addition, advanced semi-conductor technology has improved the speed and increased vastly the quantity on-chip transistors that are available to the circuit designers. Before, the designers of a computer had taken advantage of such resources in order to improve the uniprocessor structures due to its simple programming model as compared to the distributed structures of systems. However, the consumption of power and delay of wires have of late limited the continuing scaling of uniprocessor systems that make the chip multiprocessor to be more appealing. In addition, the network on chip (NoC) became the paradigm that emerge for communication within wider chip systems of multiprocessor in order to overcome delay, power, scalability, as well as issues with worldwide interconnects(Liu, et.al., 2014). However, Network on Chip (NoC) has always been implemented with a packet-based communication instead of cores that have bus connections in between. Although Network on Chip (NoC) is a good solution for a communication that are long-distance in nature, local buses prove to be more efficient for connections that are short-distanced. Additionally, Hybrid network on Chip (HNoC) fabric that use these local buses for nearer-neighbor communication and the NoC topology standard for the worldwide interconnection proves to be far better than the NoC. Perhaps, the local buses are designed to carry all the nearer-neighbor traffic, hence minimizing traffic on the worldwide network that result in rising throughput and minimize energy consumption (Somasundaram & Plosila, 2012). Therefore, it can be argued that Hybrid Network on Chip is better than the traditional Network on Chip. Body Structure In today’s life, the interconnects of chip multiprocessor applies packets witching networks in order to connect the cores. However, inter-processor messages are always broken into packets that are routed through the switches of the NoC. However, as the cores numbers rise, power consumption and performance of NoC always degrade significantly due to high costs of communication (Somasundaram & Plosila, 2012). Additionally, transferring of data from one of the core to the other through the NoC fabric, firstly it has to be packetized, and then it is sent to the router that transmits, passed through the wiring channel of the network, delivered to receiver router, and then finally depacketized. Therefore, this leads to an inefficiency in communication for a shorter distance transmission of data (Somasundaram & Plosila, 2012). HNoC was constructed by replacing some of the routers with Wireless Routers (WR) that have wireless links to other routers on top of the original wired links. Therefore, Wireless Routers are capable of making packets transferring through both wireless channels and wired signals. To differentiate the two types of routers in HNoC, in Hybrid Network on Chip, it is divided into many subnets that have one Wireless Router that is responsible for offering wireless communication in the same subnet. Allocation of Wireless Router in subnets is a significant issue to decide the performance of the system (Liu et.al. 2014). However, due to the availability of many channels, a technique of Frequency Division Multiple Access (FDMA) is always adopted for channelization to attain simultaneous diverse communications between Wireless Routers. Every receiver and wireless transmitter pair apply an independent carrier frequency in order to accommodate data from other different channels (Somasundaram & Plosila, 2012).Hence, based on the Communication Probability Density (CPD) role that is derived from the Rents rule, it has been shown that in chip multiprocessor in every 25-core, HNoC is capable to eliminate close to 78% traffic from the worldwide NoC topology that results to higher throughput and a 58% reduced in consumption of energy as compared to Network on Chip (NoC). Delivery of data in HNoC is done by a packet switching wormhole, and this is because it has the advantages of both low buffer and low transfer latency requirement. The composition of the packets is 64-bit flits. However, the first flit of a packet normally the header flit that can carries control data/ information for delivery packet such as packet type, destination address, sequential number, some control flags, and payload size. The body flits that follow the header flit are the real payload. In addition, the address ID in HNoC is described by four bit fields: Y local, X subnet, X local, and Y subnet and the two first fields are applied in specifying the location of the subnet as well as the remaining two fields is used in identifying the location of the router within a subnet (Carrillo, 2013). In terms of scalability, it is always expected that the cores numbers would increase with the scaling of the technology. HNoC can be scalable, and it provides better performance and power even in a chip with most cores. In Network on Chip,scaling of technology would result to limitations for instance long wiring delay and world synchronization as a chip dimension inceases with the majority of cores integration on a chip (Carrillo, 2013). Although the advantageous of HNoC over NoC is shrinking as the number of cores is growing, the energy improvements and throughput are considerable even for bigger multiprocessor systems (Carrillo, 2013). HNoC topology, where nearer-neighbor communications are always carried by the local bus interconnects rather than the mesh NoC. The local bus does connections that are direct between neighboring cores that are dedicated for exchanging of direct data without any of the packetizing overhead. The latency and energy consumption of short distance communication through local buses are, therefore, very smaller compared to those through NoC fabric (Ganguly et al., 2014). The local and subnet separation of an address enables fast routing decision and can easily attain scalable a design hierarchical system. Moreover, it lowers the complexity of the hardware and simplifies router design. By use of on-chip antennas, Hybrid network on chip (HNoC) is utilizing both the wired communication and intra-chip wireless as well as the resources to intelligently collaborate transmission of data among the cores in improving the performance of a system (Ganguly, 2011). Also, Hybrid network on chip (HNoC) routers offer sophisticated routing scheme in order to maintain power needs and minimal transfer latency. In addition, HNoC is viewed as a network that is formed by adding the expressways (wireless links) to baseline mesh network, and a problem can emerge on whether a packet applies the expressway or it is not. For packets whose destination and source node are located in the similar subnet, there is no need to apply wireless links. However, for packets whose source and destination node are from diverse subnets, in a design, the path selection scheme is a role of traveling distance that is expressed in hop count terms and status of buffer utilization. However, Network on-chip interconnects that carries signals across various components has been the bottleneck in its performance and reliability of the entire system, especially when CMPs is scaling to thousands or less like hundreds of cores on a chip (Ganguly, 2011). In addition, optical links face technological problems such as the design of efficient receiver and transmitter components, reliability of the integrated light source and high cost of manufacturing that prevents its functionality and in turn commercial adoption. However, these disadvantages prevent interconnections of optical from becoming a solution that is feasible. This proves beyond doubt that HNoC is better than HoC and it has already been replaced. Multihop Network on Chip channels that are wired have been already replaced with a high-bandwidth and single-hop wireless channels that is long range so that power consumption long distant communication and transmission performance challenges of traditional wired Network on Chips can be simultaneously addressed (Liu, et.al., 2014). HNoC platform was developed by a cycle-accurate simulator that is System-C based. The simulator applies a 100-core based system that divides into subnets that are four. However, each subnet consists of a channels that are high-speed wireless and 5x5 mesh network to the neighboring subnets. Also, each of the subnets employs 24 Baseline Router and one Wireless Router that features transmission that is one-hop. In addition, the simulator also features diverse configurations network for instance: topology, network size, routing algorithm, buffer size, traffic patterns generation and priority scheme for the router arbitration. Moreover, the HNoC simulator has a traffic generator that is capable of producing both application and synthetic traffic patterns unlike the NoC. For the synthetic traffic: HNoC has bit complement, matrix transpose bit reverse, and random patterns (Liu et.al. 2014). Common Ideas Firstly, it can be seen as Network-on-Chip (NoC) were built upon the metal interconnect channeling wires in order to meet the ever stringent performance needs in technological nodes. However, in response to the interconnection problems that are associated with NoC, the wireless Hybrid Network-on-Chip (HNoC) has enabled the availability of miniaturized on-chip antennas and transceivers and this is envisioned has one of the most revolutionized approach and best alternative. In addition, Hybrid Network-on-Chip(NoC) has emerged as a backbone of communication that enable a high level of integration in a multi-core system-on-Chips (Liu et.al. 2014). However, conventional Network on Chip is portrayed relying on multi-hop packet-switched communications, where a data packet is required to pass through a number of routers or switches with a considerable latency and power implications. Due to transmission range that is limited, the wireless nodes that are contained in the wireless network always communicate with one another in a set of multiple fashion. As a great volume of the traffic would pass through the wireless nodes a form of contention routing avoidance algorithm is preferred and adopted (Liu,et.al., 2014). Gaps At the moment localization traffic is obtained, Hybrid Network on Chip (HNoC) can improve significantly the usage of energy as well as performance of a system by directing the local communications through the high-bandwidth, low-power, and low-latency local buses and therefore, leaves the worldwide communications to the standard of NoC topology. In practice, in order to achieve this locality can be somehow challenging. Moreover, though some of the applications can communicate in a fashion that is localized at every point in time, at times a neighbors threads can change in due course, that can require runtime re-mapping as well as movement of a significant data. Therefore, when there is a large burst of communications that are long-distance, the HNoC local buses cannot be able to offer significant support (Somasundaram & Plosila, 2012). However, on over time and average, HNoC would support communication that are long-distance indirectly by eliminating the traffic of local communication from the NoC mesh, hence leave the mesh NoC to be fully dedicated to the long-distance traffic. In addition, besides capacity of bandwidth, the HNoC network needs a very simple wireless transceiver in order to attain the low power that can satisfy the stringent requirements of HNoC design in future (Somasundaram & Plosila, 2012). In addition, consumption of the energy can be minimized by the introduction of the local buses and the CPD can be applied in the computation of the reduction of the energy rate in HNoC. Applying the NoC energy model and assuming that the consumption of power of routers is dominant, the consumption of energy of the HNoC against the conventional NoC for the same throughput potentially, can be minimized (Ganguly A., et al. 2014). Conclusion It can be concluded that HNoC is better than NoC. It has been discussed that the local buses can carry all the traffic that are nearest-neighbors, minimizing traffic on the world network, that results in throughput increment and dropped consumption of energy. In addition, based on the CPD function that is derived from the Rents rule shows that HNoC can improve significantly the throughput as well as minimizing the HNoC consumption of energy. On one hand, transmission tasks acceleration can contribute to average dropping of latency and keep on improving the energy consumption of the tasks themselves that can be fully exploited in order to optimize the energy consumption of a system (Liu, et.al., 2014). Finally, short and active time can enable a system to enter a mode that is the power saving early in order to lower the overall system of energy consumption for the remaining transmission time of data. References Ganguly A., et al. (2014). CDMA Enabled Wireless Network-on-Chip. ACM Journal on Emerging Technologies in Computing Systems (JETC), 10 (4), DOI>10.1145/2536778. Ganguly, A., (2011). Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems. Journal of IEEE Transactions on Computers,60(10), 1485 – 1502. DOI:10.1109/TC.2010.176 Liu, W., et.al. (2014). On-Chip Hybrid Power Supply System for Wireless Sensor Nodes. ACM Journal on Emerging Technologies in Computing Systems (JETC), 10(3). DOI >10.1145/2492683 Carrillo, S., (2013). Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations. IEEE Transactions on Parallel and Distributed Systems, 24(12), 2451 – 2461.DOI 10.1109/TPDS.2012.289 Somasundaram, K., & Plosila, J. (2012). Deadlock free routing algorithm for minimizing data packet transmission in network on chip. International Journal of Embedded and Real- Time Communication Systems (IJERTCS), 3(1), 70-81. DOI: 10.4018/jertcs.2012010104 Read More