Operating Systems and Networking - Coursework Example

Computer sciences and information technology Operating systems and networking Question Instruction Set Architecture 1.1. Define instruction set architecture. Use examples to assist your answer Instruction set architecture refers to the part of a computer processor that can be seen by the programmer or a person who writes compilers. The instruction set architecture usually acts as the boundary that is between the software and the hardware of a computer. It is the interface between the software and the computer hardware. It provides the means with which the software communicates with the hardware to tell it what to do. Instruction set architecture can best be described using five categories: The Operand Storage in a CPU – this is used to explain where the operands in computer processes are stored apart from the memory The number of the explicitly named operands - how many named operands are there in a typical instruction?. The location of the operands – can operands used in ALU instructions be kept in the memory? Alternatively, can all the operands be stored internally in the central processing unit? The operations of the instruction set architecture – which operations do the instruction set architecture support? The size and type of operands – what is the size and the type of every operand that is used by the instruction architecture?. Also, how are they specified? From the above categories, only the first category stands out as the best factor to use to distinguish the instruction set architecture. Of all ISAs known, the following 3 are the most common: 1. The accumulator – a single operand is implicitly the accumulator 2. The stack – operands are on top of the stack 3. The general purpose register (the GPR) – every operand is mentioned explicitly. They can either be memory locations or registers. 1.2. A processor has 32 bit instruction format with the following fields: opcode: 8 bits ra: 6 bits rb: 6 bits rc: 6 bits rd: 6 bits where ra, rb, rc, specify three input registers and rd specifies one destination register. If there is a single register file to store the identifications of all registers, how many registers could there be in that register file? The number of registers in the single register file would be = 26 = 64 This is computed from: the number of registers = 2|the number in the register fields| 1.3. A processor has 24 registers, uses 8-bit immediate, and has 36 different instructions (corresponding to 36 operation codes) in its instruction set. These 36 instructions are classified into 4 types as listed below: Type A: takes 2 sources register, uses 1 destination register; Type B: takes 1 source register, uses 1 destination register; Type C: takes 1 source register, 1 immediate, uses 1 destination register; Type D: takes 1 immediate, uses 1 destination register Assume that the ISA requires that all instructions be multiple of 8 bits (1 byte) in length, and the operation codes (opcodes) are fixed length. Answer the following questions and write down the calculation steps involved. a. How many bytes do we need to use to encode the Type-A instruction? 24 registers require 5 bits ( 0 - 31). 36 operation codes require 6 bits ( 0 – 63 ) Therefore Type A instructions that require 2 source registers and 1 destination register will need: Type A: 6 bits operation code, 5 bits register, 5 bits register, 5 bits register = a total of 21 bits which are then rounded up to 24 bits which is equivalent to 3 bytes since 8 bits equal to one byte b. How many bytes do we need to use to encode the type C instruction? The type c instruction takes 1 source register, 1 immediate, and uses one destination register. It will require: Type C: 6 bits of the operation code, 5 bits for the source register, 8 bits of the immediate, and 5 bits of the destination register. This totals to 19 bits. These are rounded up again to 24 bits. 24 bits are equivalent to 3 bytes. Therefore 3 bytes are required to encode type c instruction. Question 2: pipelining Assume that a pipeline processor operates in four states: instruction fetch, operand fetch, operand execute, and operand store. A timing diagram of pipeline could be drawn as follows: Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 … … IF ADD R1,R2,R3 Table 1. Example timing diagram 2.1. Suppose we have the following code with the data dependency. ADD R1,R3,R2 [R1] ← [R3]+[R2] SUB R4,R1,R5 [R4] ← [R1]-[R5] MUL R6,R7,R8 [R6] ← [R7]*[R8] Draw a timing diagram (like Table 1) for the above simple code sequence. Explain how the pipeline mechanism works in this case and how much the speedup ratio would be. Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 … … IF ADD R1,R2,R3 IF OF OE OS SUB R4,R1,R5 IF OF OE OS MUL R6,R7,R8 IF OF OE OS Table 2. solved timing diagram The pipelining diagram is used to show the execution of a series or a sequence of instructions of processes of a computer. In the diagram, the sequence of instructions is shown vertically; that is from the top to the bottom. As for the clock cycles, they are often shown in the horizontal; that is from the left to the right. Each and every instruction is divided into its component stages. For the diagram above, the instructions are divided into 4 steps or stages of processing. Each instruction has 4 stages. This makes it easy for the control unit to do the processing. Pipelining enables computers to do more than one instruction processing at a time. Each instruction is divided into components which are then executed in stages as shown by the diagram above. There are 3 instructions. Suppose a non-pipelining processor took 50 Nano seconds to process one instruction, and then it would take 3 * 50 = 150 Nano seconds to complete all the instructions. However when pipelining is used, we instead have 4 segment pipeline with a clock cycle that takes at least 10 Nano seconds approximately. For the three tasks, the speed up ratio would be: Time taken with pipeline = ( 1 * 4 * 10 ) first task takes full pipeline time of 4 stages + ( 3 * 10 ) rest of the tasks take 1 stage time each The total time comes to = 40 ns + 30 ns = 70 ns Therefore the speed up ratio = 150 / ( 40 + 30 ) = 150 / 70 = 2.14 2.2. Suppose we have a slightly more complex program with data dependency and branches. Assume that in the case of branching, the instruction following a branch is always executed. Note that a conditional branch instruction is resolved during its ‘operand execute (OE)’ phase, which means the target address of the next instruction may only be available in the following cycle. In that case, a BEQZ X (branch to X if zero) or BNEQZ X (branch to X if not zero) instruction could use. ADD R1,R3,R2 [R1] ← [R3]+[R2] SUB R4,R1,R5 [R4] ← [R1]-[R5] BNEQZ R4, X If zero THEN goto X MUL R6,R7,R8 [R6] ← [R7]*[R8] ADD R1,R4,R2 [R1] ← [R4]+[R2] SUB R4,R5,R7 [R4] ← [R5]-[R7] X MUL R3,R1,R3 [R3] ← [R1]*[R3] ADD R2,R6,R2 [R2] ← [R6]+[R2] SUB R1,R2,R5 [R1] ← [R2]-[R5] Read the code sequence above, draw a timing diagram (like Table 1) for a pipelined solution. Explain how the pipeline mechanism works in this case and how much the speedup ratio would be. Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 Cycle 12 ADD R1,R3,R2 IF OF OE OS SUB R4,R1,R5 IF OF OE OS BNEQZ R4, X IF OF OE OS MUL R6,R7,R8 IF OF OE OS ADD R1,R4,R2 IF OF OE OS SUB R4,R5,R7 IF OF OE OS MUL R3,R1,R3 IF OF OE OS ADD R2,R6,R2 IF OF OE OS SUB R1,R2,R5 IF OF OE OS For 9 instructions or tasks, the total time would be 9 * 50ns = 450 ns With pipeline = 1*4*10 + 8*10 = 40 + 80 = 120 ns Speed up ratio = 450 / 120 = 3.75 Bibliography Shanley, T 2012, x86 Instruction Set Architecture, First edition edn, MindShare Press, New Jersey. Read More