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Digital System - Assignment Example

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Since the basic design involves the use of D flip-flops, let's see what the basic D-flip-flop is like and how it functions. A D flip-flop is a latch constructed from an SR latch. It has two additional AND gates, and a NOT gate. There are two ways to input into this flip-flop, one is the data input (D) and the other is the gate (G) or enable (E) input.
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Digital System
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Download file to see previous pages For example, D flip-flops have been used in the 7400 series of integrated circuits.
The Algorithmic State Machine (ASM) is a method that is used to design finite state machines. It is used to show diagrams of digital integrated circuits. The ASM diagram is like a state diagram but less formal and thus easier to understand. State machines are functional forms of application planning. When an application is developed, its complexity also increases, state machine diagrams help to accommodate such complexities in the design easily. Creating an effective State Machine requires the designer to make a table of all possible states. With this table the designer can plan how each state is related to another. The design process involved in creating an operative State Machine will also improve the overall design of the application.
If the above application has to work without problems, the design must be kept as simple as possible and it must be modular. It is important to implement one module at a time, and test each module. While building the design, it is important to be aware of clock skew and use similar path lengths to all flip-flops. Gated clocks, must be avoided and all positive-edge-triggered or all negative-edge-triggered flip-flops must be used in the design.
It is important to keep track of asynchronous inputs to the circuit and better to avoid such inputs altogether. If such inputs cannot be avoided, it is better to synchronize them. The use of debounced switches will help to provide clean input signals. All flip-flops must be initialized to known values at the beginning and the dependencies on minimum logic gate delays must be avoided.
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