Microprocessor of the Intel Company - Essay Example

80286 Microprocessor The 80286 was introduced by Intel on February 1982. The 80286 was Intel's next step processor for micro computers. The most substantial difference between the 80286 and the 8086/8088 is the addition of a protected mode. The 80286, or in short 286, had a 16 bit design and could address the enormous amount of 16 Megabytes of RAM. Unfortunately with that feature the processor was not backwards compatible with older processors and software that was written for these older CPU's. Because that backward compatibility was very important for the commercial success of the 286, Intel came up with a trick: Real-mode and Protected-mode. When a PC with a 286 booted, it booted in the Real-mode just like every XT would. In that mode the 286 could only address 1 Megabyte of RAM. The software could then switch the processor in Protected-mode; the 286 could now address the full 16 Megabytes of RAM. Once the processor was switched to Protected-mode it could only switch back to real-mode by resetting the CPU, i.e. rebooting the PC. Looking back at that time and thinking of all those who had a 286, the software they ran just a really fast XT. Among other things, protected mode allows safe execution of multiple programs at once by protecting each program in memory. DOS normally operates in real mode, in which segment registers act just as they do in the 8086/8088. Protected mode is used by Microsoft Windows, IBM's OS/2 and UNIX. With the 80286, the first "chipsets" were introduced. The computer chipset is a set of chips that replaced dozens of other peripheral chips while maintaining identical functionality. Chips and Technologies became one of the first popular chipset companies. Intel second-sourced the 80286 to ensure an adequate supply of chips to the computer industry. AMD, IBM, and Harris were known to produce 80286 chips as OEM products; while Siemens, Fujitsu, and Kruger either cloned it or were also second-sources. Between these various manufacturers, the 80286 was offered in speeds ranging from 6 MHz to 25 MHz. Intel added four more address lines to the 8086/80186 design. The 8086, 8088, 80186, and 80188 all contained 20 address lines, giving these processors one megabyte of addressability (2^20 = 1MB). The 80286, with its 24 address lines, gives 16 megabytes of addressability (2^24 = 16 MB). The 286 was designed to run multitasking applications, including communications (such as automated PBXs), real-time process control, and multi-user systems. The 80286 contains a total of fourteen registers that are of interest to the application programmer. These registers may be grouped into four basic categories: General registers. These eight 16-bit general-purpose registers are used primarily to contain operands for arithmetic and logical operations. Segment registers. These four special-purpose registers determine, at any given time, which segments of memory are currently addressable. Status and Control registers. These three special-purpose registers are used to record and alter certain aspects of the 80286 processor state. For descriptive purposes, the 80286 instruction set is partitioned into three distinct subsets: the Basic Instruction Set, the Extended Instruction Set, and the System Control Instruction Set. The "hierarchy" of instruction sets defined by this partitioning helps to clarify the relationships between the various processors in the 8086 family . Five of the general- purpose registers are available for offset address calculations. These five registers, shown in figure 2-4, are SP, BP, BX, SI, and DI. SP is called a pointer register; BP and BX are called base registers; SI and DI are called index registers. The Basic Instruction Set, comprises the common subset of instructions found on all processors of the 8086 family. Included are instructions for logical and arithmetic operations, data movement, input/output, string manipulation, and transfer of control. The Extended Instruction Set, consists of those instructions found only on the 80186, 80188, and 80286 processors. Included are instructions for block structured procedure entry and exit, parameter validation, and block I/O transfers. The System Control Instruction Set, consists of those instructions unique to the 80286. These instructions control the Memory management and protection mechanisms of the 80286. Call gate descriptors are used by call and jump instructions in the same manner as a code segment descriptor. The hardware automatically recognizes that the destination selector refers to a gate descriptor. Then, the operation of the instruction is expanded as determined by the contents of the call gate. A jump instruction can access a call gate only if the target code segment is at the same privilege level. A call instruction uses a call gate for the same or more privileged access. The information encoded in an 80286 instruction includes a specification of the operation to be performed, the type of the operands to be manipulated, and the location of these operands. If an operand is located in memory, the instruction must also select, explicitly or implicitly, which of the currently addressable segments contains the operand. The five elements of a general instruction are briefly described below. The opcode is present in all instructions; in fact, it is the only required element. Its principal function is the specification of the operation performed by the instruction. A register specifier. The addressing mode specifier, when present, is used to specify the addressing mode of an operand for referencing data or performing indirect calls or jumps. The displacement, when present, is used to compute the effective address of an operand in memory. The immediate operand, when present, directly specifies one operand of the instruction. Of the four elements, only one, the opcode, is always present. The other elements may or may not be present, depending on the particular operation involved and on the location and type of the operands. Generally speaking, an instruction is an operation performed on zero, one, or two operands, which are the data manipulated by the instruction. An operand can be located either in a register (AX, BX, CX, DX, SI, DI, SP, or BP in the case of 16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit operands; the FLAG register for flag operations in the instruction itself (as an immediate operand)), or in memory or an I/O port. Immediate operands and operands in registers can be accessed more rapidly than operands in memory since memory operands must be fetched from memory while immediate and register operands are available in the processor. The 80286 base architecture was designed to support programming in high-level languages, such as Pascal, C or PL/M. The register set and instructions are well suited to compiler-generated code. The addressing modes allow efficient addressing of complex data structures, such as static and dynamic arrays, records, and arrays within records, which are commonly supported by high-level languages. The data types supported by the architecture include, along with bytes and words, high level language constructs such as strings, BCD, and floating point. The memory architecture of the 80286 was designed to support modular programming techniques. Memory is divided into segments, which may be of arbitrary size, that can be used to contain procedures and data structures. Segmentation has several advantages over more conventional linear memory architectures. It supports structured software, since segments can contain meaningful program units and data, and more compact code, since references within a segment can be shorter (and locality of reference usually insures that the next few references will be within the same segment). Segmentation also lends itself to efficient implementation of sophisticated memory management, virtual memory, and memory protection. References: 1. Microprocessor Hall of Fame. 2 INTEL 80286 PROGRAMMER'S REFERENCE MANUAL 1987 3 Rosenblum, Mendel; Garfinkel, Tal (May, 2005). "Virtual machine monitors: current technology and future trends". Read More