Fast Fourier Transform - Essay Example

A second approach includes just a single hardware operator of the butterfly type, and intending to perform in succession the computations corresponding to all the butterflies of all the stages of the graph. Such an approach has the drawback of requiring a very fast hardware operator. An input memory separate from the memory is required for writing the intermediate computation results. This avoids access conflicts when a data block enters the operator while the previous block is still being processed.

It is therefore necessary to provide two memories of N0 complex words, where N0 denotes the initial size of the Fourier transform. This leads to an overall circuit of considerable size, especially when N0 is large. An intermediate approach includes a hardware operator of the butterfly type per stage of the graph, as well as a storage element. This includes delay lines or shift registers, whose function in to input the data to the operator in the right order, while aware of the butterflies of the graph of the relevant stage.

Such architectures are termed serial or pipelined according to terminology well known by one skilled in the art. More precisely, an electronic device for computing a Fourier transform having a pipelined architecture comprises a plurality of successive processing stages connected in series between the input and the output of the device by internal data paths. These stages respectively comprise processing means and storage means. The processing means performs processing operations for Fourier transforms of smaller elementary sizes than the initial size on blocks of data whose sizes are reduced in succession from one stage to the next.

The term "initial size" of the Fourier transform is understood here and in the remainder of the text to mean the size of the blocks received as input to the device by the first stage. The elementary sizes of the Fourier transforms performed by the various stages may be identical and equal to the radix of the Fourier transform; i.e., a Fourier transform with uniform radix. However, they may be different from one stage to another, as in the case of Fourier transforms with mixed radix.US Patent No.

6,098,088 discloses Fast Fourier Transform processor architecture, based on radix-22 single path delay feedback (R22SDF) architecture. Input data is applied to a series of pairs of butterfly means, each pair including a first type of butterfly and a second type of butterfly, with each having a feedback path from its output to its input. Until the end of the series is reached, the output of the second butterfly in each pair is applied to a multiplier, before the multiplier output is applied to the first butterfly in the subsequent pair.

In order to be able to use Fast Fourier Transform processor architecture in a data communications system such as an OFDM Ultra Wideband (UWB) communications system, the processor must be able to handle a high data rate. Moreover, the hardware cost of the processor is an important factor. According to a first aspect of the invention, there is provided an apparatus for performing a Fast Fourier Transform operation, the apparatus comprising: an input, for receiving input data; a plurality of first data processing paths, each being adapted to perform said Fast Fourier Tran