The Sampling Process of a Motor Speed - Essay Example

Design of a Motor Speed Sampling, Amplification, Filtering and Display Circuit _____________________________________________________________________________________Digital and analogue electronic By Hamed Al-Mulla Student Id: 672743 Abstract The document in here has been generated at my modules’ request. However, the primary attention of the paper is handling as well as the processing of small signals. A current signal is employed in the study as a major a supply. There were various mechanisms that were used in the generation of this signal. For instance, it applied the use calculations, computer simulations as well as graph analysis. The main findings of this particular will contain a fully operational diagram that will include every single step of processing the signal. Contents: 1. Abstract/ Acknowledgements ……………………………..1 2. Contents ………………………………………………….2 3. Introduction, Objectives………………………………….3 4. Procedure…………………………………………………4 5. Readings………………………………………………….4 6. Calculations………………………………………………5 7. Graphs…………………………………………………….5 8. Results……………………………………………………21 9. Discussion……………………………………………….31 10. Conclusion……………………………………………….31 11. References……………………………………………….35 Introduction Current world technology enables different mechanisms to be conducted; the estimation of a motor speed is given as a small AC indicator. In these Lab findings, the evaluation as well as processing of the signals is done through various techniques that can be expressed on a seven segment display. Therefore, for the process to be meaningful, it needs to employ different reliable stages of amplifications, as well as conversion. In order to attain these intensifications there are various number of means that one can use, some can be very simple while others can be perplexing (Van der Spuy, 2012). The findings will give a primary basis in the comprehension of various circuits as well as some major Analogue components. In addition, it will ensure there is the proper understanding of Proteus that is the computer simulation equipment. Objectives The principal intention of the research is to carry out the sampling process of a motor speed. The strategy of an amp is to be produced. The range of the current sample will have the following range. That is; from -2.5 to 2.5 m Amplifier. The initial step was to change the signal from that particular current to signal voltages that range from 2 – 3 Volts. The following step requires the filtration of the signal by employing a low pass filter and avoiding any signal that operates over 100 Hz. After the completion of this particular phase, there will be diversification of focus to the digital side of the circuit. There will also be the employment of an analogue converter that is the A 8 bit to change the current voltage signal into an eight-bit digital signal. There will also be processing of eight bit signal to give a two-bit indication in bit hex decimal on the two seven section showing devices that indicate the moving speed of that particular motor in 0-255 scales. Procedure, readings and calculations In this particular section of the findings, the process indication as well as the workings calculations are all carried out together. The complete scheme has been subdivided into different parts, the analogue part and the digital part. The analogue part has been split into different sections, and every partition will be needed in the respective amplifier taking as a first major step in the conversion process. However, there was analysis as well as calculations of the individual procedures before carrying out the following steps; First procedure: In this section, the first phase is the part of amplifier conversion of the current pointer into a voltage signal. However, the part of the circuit will be reached at through the employment of an op amp circuit. The stream will be -2.5 to 2.5 m Amp. The op amp route and the computations as indicated below: In the above illustration, V0 is the virtual earth section with denotation of (V_). However, the section contains the maximum voltage of zero.  Therefore,  Therefore, since V_ is equal to zero, Ir ill be as follows:  thus Having different arrangement will be the output voltage in this circuit is directly proportional to the opposite current that is the input current. The negative sign shows that the output current is proportionate to the input voltage. On the other hand, in the simple gain, the ratio has the current that is resistance. The circuit is known as a trans-resistive amp. From the formulas above, there is a demonstration that Vo/Ii=-R indicate the ratio. From this method, one can compute the output current of 2-3 volt. In order to efficiently attain this, one is supposed to have an AC output that ranges from 0.5 v ±. In order to accomplish this objective, and then the current resistor needs to be: 0.5=2.5*10^-3*R-> R=200. In addition, there will also be an exhibition of the ISIS simulation as below. The circuit shows that that the current input is 0.0025 amps, and the current output is ±0.5, on top of the 200 thus boosting the conversion process. Fig 2.0 The calculation of Zin is through: = Rf / (A+1) = 200/ (100000+1) =0.m Ohm, making it a very minimal resistance of an internal for an op amp. The value is tiny in that it cannot be given much consideration. The reason is that, the input Z is at the virtual base. Therefore, the output impertinence will be at infinite. That will be shown in the graph below. 2.1 2.2 The addition of an extra part of the circuit will not change the internal resistance. Instead, it will remain at the value of 1, fig 1 The diagram below shows the extermination of the circuit from the indication in the output. The current will have the representation of the green line; the green line has the values that range from point of 0.5 positive and negative. It is the amount arrived from above confirming that the circuit is correct and working. Figure 2 The next process is the addition of 2.5 V as DC bias. The above addition will enable out the circuit to convert the value of output between the volts of 2 and 3. For the system to be efficient, one will have to join a current divider to 2.5 v DC value with the positive side of that particular op amp. The Proper explanation is shown in the ISIS diagram below. (Fig 3). In order to arrive at 2.5 than the overall resistance needed, and then it will be as follows: 15 =2.5*Rt, Rt is 0.16. However, in calculating the total resistance, the following method will be employed. That is; R2/ (R1+R2). The method will now lead us to the attainment of 2K for R2 and ten k for R1. In addition, the other values than can be employed include values like 20k and 100k. The values will still lead to the same outcome. That is the ratio that ranges between R3 and R2 should be 5:1. Figure 3 The addition of DC bias to the circuit will change the output to range between 2-3 volts. The diagram below explains the conversion analysis. Step two The addition of the filter is the next step; it is because it has the frequency that is above 100, making more noises. The circuit preference is as below. The ISIS diagram is shown bearing the total analogue circuit as indicated below For the above circuit G(s)=2.5/s+2.5, the figures for particular components are arrived at 1K ohms for R as well as 1.6u F for the capacitor. Therefore, it will enable a short of the frequency of 99.5072 H z. The analysis diagrams are as below. The impudence of the capacitor will reduce with an increasing frequency. The lower impedance in the parallel lane with the load resistance will tend to cut out high-frequency signals, leaving most of the current across series resistor R1. In addition, it is shown in an ISIS graph below. One can explain the cut of the frequency to be around 100Hz. It is because it was supposed to have a frequency cut-off of 100Hz. However, the circuit bandwidth will have to be 0 to 100Hz. The calculation of cut-off frequency in this scenario will be 99.47 Hz after the addition of the capacitor. The illustration of op amp bandwidth is shown in the graph below as1.09MHz. The employed filter is a reliable option, cost effective and low requirement of space. Other different filters can be employed to boost the efficiency of the cut-off frequency. For instance, an initial Order more inferior pass filter has an Op Amp. Therefore, it will give it an ability to display a basic set up of the circuit. The mechanisms used to derive the frequency are as shown below. The diagram below is a display of a sweep of noise, bearing the green trace representing the level of noise before the filter as well as the read trace of the signal after the filter. Step three is the digital section of circuit The following section of the graph converts an analogue signal into a digital signal. In this section, an A to D converter will be employed at 8 bit, as it will be shown in the diagrams below. The above diagram or component has an energy transmitter of 15 V as indicated in the diagram. The eight impacts will have a connection with the two different of the four to 7 segment converters. Therefore, bearing the connections will range from D0 to D3 that will be connected to the first converter. However, the second converter will get the left connections coming from D3 to D7. At this section, CKL as well as HOLD connections of the A to D exchangers is interconnected to a counter. The counter has a D-type flip-flops design that enables it to be driven by a CLK signal passing through 256k Hz. The plan below shows a basic diagram of a D-type flip-flop and its operations. The clock is another good example of the operation of an output circuit. The diagram below displays, a general production lay from an output of the clock. The clock has the indication of 256k as the result of the eight-beat counter. However, the clock is supposed to have an eight beat timer. Full evidence, as well as an explanation, is as shown in the figure below. There has been the removal of component tags because there are various that caused duplication of names. The next step that will follow in this project will be the designing of a 4 to 7 segment converter. However, to conduct this zero components will have to be active, and one will have to be the off component. The below table is done bearing all the needed values In this section the karnaugh map for every letter of the seven segment exhibition is generated as shown below: A = 0001 0100 1011 1101 ABCD ABCD ABCD ABCD B= 0101 0110 1011 1100 1110 1111 ABCD ABCD ABCD ABCD ABCD ABCD E= 0001 0011 0100 0101 0111 1001 ABCD ABCD ABCD ABCD ABCD ABCD F= 0001 0010 0011 0111 1101 ABCD ABCD ABCD ABCD ABCD Because there are three categories in the Kano graph the prescriptions can be cut down by cancelling out BCD Final Formula = ABCD + BCD + ABC + ABD + ACD C = 0010 1100 1110 1111 ABCD ABCD ABCD ABCD Final Formulae = ABCD + ABD + ABC D = 0001 0100 0111 1010 1111 ABCD ABCD ABCD ABCD ABCD Final formulae = ABCD + ABCD + BCD + ABCD G = 0000 0001 0111 1100 ABCD ABCD ABCD ABCD Finale Formulae = ABC + ABCD + ABCD From the map that is the karnaugh map, one can formulate the bullion explanations for the required communication. From the prescriptions, the following step will be to design the circuit, a design of letters are shown in the below graphs. The first process is designing the supply sections. That is; section, A, B, C, D and the NOT section foe every for each connection. The point is taking the required connections for the designated communications. Figure 15- Letter H Figure 16- letter I Figure 17-Letter j Figure 18-Letter K Figure 19-Letter L Figure 20-Letter M Figure 21-Letter N In this section, after all, the letters have been designed, the next procedures the connection of the letters and synchronizing them with the seven segments display as shown in the figure below. Figure 22 Connection of letters 4 to 7 converter is the next step, for it needs to have two 7 section displays the first set will be derivative and employed. The connections will be implemented as indicated in the figure below. Figure 23 The two screens are set situated in parallel and the same time program is running, the values go in the range of 66 and 99. Discussion In this research had some few downfalls experienced in the entire process of connection and current flow. However, there will be an adequate explanation of these challenges in this section. The first section to deal with will be the digital side of the report. In this case problem that emerged was to include the DC bias to the converter AC signal. Different techniques were verified, for instance; the output converted current from the op amp. It was linked with a transistor circuit that was primarily designed to include a DC bias to a small pointer. Also, the channel was colossal and to various components where required therefore calling the necessity of an alternative mechanism. Moreover, a current divider was generated taking 15v from the sequence, and linked to the output of the op-amp via the capacitor. However, the set up proved positive but it removed the conversion in the output as per the input ratio. The next section of the circuit is related to the filter. One had to conclude on what type of filter was the most reliable option for the course. There are hundreds of different screen setup`s that can achieve the same results but with small differences. The relaxation of the outcome is usually specified at a higher. However, in this case, the specification was only meant to the cut-off point of 100 Hz. There was no clear indication of the steepness of a particular slope as well as the exact the cut-off section had to be correctly indicated. The challenge that entire filters have is that they are not 100percent accurate therefore making it not reliable in making a decision. In a perfect region, the cutting point would be at an angle of 90 degrees from the distribution frequency, and it would be complete at the required cutoff frequency point. In order for one to attain this one will need various component values that are not existent at that particular section. Some components will include; the resistor, capacitor as well as inductor will have a tolerance value. The filter preferred was a simple Lower pass filter that contributed to most reliable results. The next section to discuss is the digital point; in the conversion of analogue to digital was not much that could go wrong. Instead, it was a primary step. The first point that could not go straight was building the clock stand signal. A basic but attractive and efficient setup was employed making the set up to be widely adopted in the industry for it can easily match to the required beats. In the digital section of the report, the major problem was encountered in the creation of the 4 to 7 segment decoder. The name was overlapping in the addition of the required gates. Moreover, another challenge was encountered while copying the full decoder and employed for the second seven segment show. In addition, the cable labels were also overlapping. Moreover, the addition problem was experienced during the letters of the show where it was designed without putting into consideration all segments. For instance, the number 7 section at the angle of the number that would make the seven look like a proper number was not incorporated. Conclusion This experiment entails all sectors of electronic design. The first section of the test includes the how a signal can be generated, by employing different component. The message can be altered and converted to meet the required values, therefore enabling the input to impact the output totally according to the ratio designed. However, the report findings show aid of op amp as employed to add DC bias to a converted power signal. The using primary component filter was generated to cut down any frequency that is beyond 100Hz. At this section, the analogue point of the circuit was completed as well as an A to D converter was installed. The converter of A to D had different outputs, as well as inputs, one of the inputs, is originating from a clock signal. The clock signal was generated to convey a 256k Hz signal. It was made using various gates; 8 D latch flip flop were employed in different designs the necessary 8 bit counter. In addition, the findings of the A to D converter a 4 to 7 section table were created by employing the gates. In this process, the final decision is that with the aid of various components set ups can be generated to attain the intended outcome. A set of elements can be employed to the diversification of setups to reach different findings, enabling the designer to convert systems values to the desired values. List of References Van der Spuy, R. (2012). Foundation Game Design with HTML5 and JavaScript. Dordrecht: Springer. Read More