Supercomputing Exaflop Target - Assignment Example

Supercomputing Exaflop Target Asia has come out leading in computer fastness in June’s 2011 top 500 list on the basis of LINPACK benchmark. Japan‘s K Computer emerged the top with 8.2 quadrillion floating points operations per second (petaflops) followed by China’s Tianhe-1A at 2.4 petaflops and thirdly the Jaguar of the US which was pushed from second place at 1.72 petaflops. Others included China’s Nebulae in fourth place at 1.27, and Japan Tsubame 2. 0 in fifth place at 1.19 coming. Scientists in the world of computers however, do not see the value of these rankings. They do not see the usefulness of the petaflops and consider the need for practicality in both preserving and taking advantage of the power (Geller, 16). Programming for the CPU or GPU combination popular in super computing is more difficult than that for the commodity CPU.Changing the codes from sequential to parallel will not be that easy as the transition might take a longer time of about 3 to 5yrs.Data delivery and correction of errors might reduce the speed of the application despite the superb programming. The GPUs has allows enormous calculations of numbers in parallel as they constitute more cores as compared to the CPUs and currently is applied to various data –intensive calculations. The GPUs was originally for tasks that are of graphics such as rendering every pixel in an image. This is because the graphic problem resembles the supercomputing problems (Geller, 16). In the modern world of supercomputing, the GPUs relies on the CPUs for other tasks despite being able to provide the highest calculation power. The speed is not a matter of throwing more cores in the given mix given that it is not easy to avail all the power used in the processing. The data ought to be managed for their proper in take and managing of the outcome. For the data to move appropriately between the CPUs and GPUs and attainment of better performance, the problem has to fit in the GPUs itself. Before the benefit is attained the speed of the moving data and that of computing are so mismatched and therefore the GPU has to undertake a number of computations (Geller, 16). The Asian researchers are well positioned to the GPUs more parallel supercomputing that is massive. It is believed that economics that favor such innovations may be brought about by China’s isolation from the western influences. This is because of the vendors from the US who holds different perceptions. Whereas the potential bang for the buck is in Asia, if an applications works effectively on this kind of accelerator technology, it might turn out to be very cost effective. China’s recent entry into HPC may be of help in this regard. In contrast it is argued that programmers in more experienced nations may have to undergo re-education (Geller, 16). Historically Hybrid architectures have had an upper hand over the parallelism. They have used less energy than comparable CPU-only systems. The new Top500 list showed that the architectural battle over energy efficiency is on. The U.S.’s CPU-based IBM Blue Gene/Q Prototype supercomputer is the most energy-efficient system with efficiency of 1,680 Mflops/watt. The K Computer consumes enough energy to power nearly 10,000 homes, and costs $10 million a year to operate. These costs would significantly increase in an exaflop world. Major changes in the hardware will require major changes in the algorithms and software. Supercomputing is already widely used in fields as diverse as weather modelling, financial predictions, animation, fluid dynamics, and data searches. Each of these fields embodies several applications. While exaflop computers will spawn now-unimagined uses, any current increases in speed as we race toward that goal will greatly benefit many existing applications (Geller, 16). Understanding Sources of Inefficiency in General-Purpose Chips Regulating the performance of any given processor that is power limited demands lowering the energy consumed in accordance with the instruction undertaken, since power is the product of energy/op and op/seconds. There are two broad strategies for a customized hardware that determines the capacity to produce general purpose chips with better efficiency. One strategy extends the present trend of creating general data-parallel engines on the processors. It is similar to the addition of SSE instructions or merging graphic processors on die to assist with other applications. The other approach creates application-specific data storage that is connected with functional units. This approach should be an ASIC-like solution in the limit. The first approach has the merit of being a solution that is programmable, while the second approach has the advantage of providing potentially greater efficiency. Lowering the energy needed for the basic operation can be attained through a number of techniques, all of which fundamentally reduce the overhead connected with the work being done (Hameed, 37). To be able to identify and monitor improvement in the processing efficiency of a 720p HD H.264 encoder, its performance and energy sources should be quantified. The IP creates a prediction for image-block that is an alternative using a past encoded close image blocks within the present image. Whereas the computations are considered to be less than motion of the estimation algorithms, the algorithm will still continue to be dominated by the arithmetic operations. The dependencies not only exist in the algorithm and are also present in the both quantization and transform functions (Hammed, 37). The initial overheads are large meaning that the CMP is 500× less energy efficient than an Application Specific Integrated Circuit (ASIC) when doing the same job. The energy consumed in instruction fetch (IF) is an overhead as a result of the programmable nature of the processors and is not present in a custom hardware state machine, but doing away with all this overhead will only increase the energy efficiency by less than one third. Eliminating these overheads by transforming the CPU into a specialized system for H.264 encoding is one of the methods that can be explored. Broadly applicable optimizations like single instruction, multiple data (SIMD) units better CMP performance by 14× and energy by 10×, which is still 50× worse than an ASIC.The limitation is that the basic operation costs in H.264 are so limited that even with a SIMD unit doing over 10 ops per cycle, 90% of the energy is still overhead(Hammed, 37). Attaining ASIC-like performance and efficiency needs algorithm-specific optimizations. For each sub algorithm of H.264, we create a huge, specialized functional/storage unit which is capable of performing hundreds of operations per instruction. This subsequently improves energy efficiency by 160× (instead of 10×), and the altemate customized CMP reaches the same performance and within 3× of an ASIC solution’s energy in comparable area. If application customization will be needed for efficiency and, that the data indicates it will be, there is need to start creating systems that will efficiently allow savvy application experts to create these optimized chip level solutions. This will mean extending the ideas for extensible processors to full chip generation systems (Hammed, 37). Work cited Geller, T. "Supercomputing's Exaflop Target." Communications of the Acm. 54.8 (2011): 16-18. Print. Hammed, R, W Qadeer, M Wachs, O Azizi, A Solomatnikov, B.C Lee, S Richardson, C Kozyrakis, and M Horowitz. "Understanding Sources of Inefficiency in General-Purpose Chips." Computer Architecture News. 38.3 (2010): 37-47. Print. Read More