Traffic Light Controller Circuit - Coursework Example

Traffic Light Controller Circuit Name: Course: Instructor: Institution: Date of Submission: Introduction The traffic light controller exists as the devices that prevent control traffic flow through traffic intersections through timing the red, yellow and green lights. The traffic lights controller are based on timing the cyclic timing of the lights. The cycle of the traffic lights repeats itself unlimited. The lights use the Tr, Ty and Tg values where the Tr is the Red Value, Ty for yellow and Tg for Green. Thus, the project will provide the logic circuit design to allow the functionality to execute. It includes presenting the logic components and the relationship that exists between the inputs and the outputs. The paper will also select the VHDL code to accommodate the traffic light controller design for the figure below. It will include the code to execute the operation of controlling the outputs and inputs to specify the operation input and output pins to produce the correct output to drive three LEDs bestowing to the input values. Methodology: Logic Design Figure 2: Logic Circuit Design Network The light circuit of traffic is used for controlling traffic (Langholz, et al., 1998). The logic design network normally has three inputs and two outputs. The inputs include count, input 1 and two while the outputs include output 1 and 0. The functions implemented by F in the design include count 0 where O1 – O0 develops to 11-10. On the other hand, count = 1 equals to (11-10) is 01 where O1-O0 develops into 10. However, when 11-10 is implemented as 11 and count=1 where the output value will not overflow as it wraps around 00 (Ward & Hatlead, 1990). Thus, the logic design of the circuits should be as follows: Full-Adder Logic Design Diagram Count 11 10 O1 O0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 0 The logic circuits designs include adders, comparators, decoders, multiplexers and encoders among others (6ch, n.d.). As presented in the diagram above, it adds the input bits and the input carry. The output carry is 1 when the inputs to the gate are 1s. The gate circuits logic designs were constructed through components such as resistors, diodes, and transistors. The circuit design at the gate level leads to the development of the physical circuit. The logic gates lead to the construction of a single integrated circuit. The 1s and 0s used in the logic design by implementing the simple Boolean functions. The development of combinational logic uses building blocks that lead to the logic design of the circuit (Ward & Hatlead, 1990). The combinational values of the inputs and outputs are used in developing the integrated circuits. The multiplexer device is used for input signals while presenting the signal to an output terminal. The Boolean variables are then used in the implementation of the mechanical motion that selects different inputs in the traffic controller device. The Boolean function is used in building the electronic analog switch (Ward & Hatlead, 1990, 106). The traffic controller needs more than one multiplexer input to choose more than one input. VHDL CODE VHDL stipulates the Very-High-speed integrated circuit Hardware Language description. The Defense Department developed it, and the language follows a formal syntax language. The VHDL mainly has three sections, which include the library declaration, entity, and architecture (Pedroni, 2005). The library declaration section deals with providing the available listed libraries a code that is already written by others but can be used in the circuitry. For instance, for the IEEE library, the following code can be used: (ieee.std_logic_1164.all;) the brackets are not necessary The code is used in the library where every unit of the code is a necessity and not optional (Pedroni, 2005). The semicolons, for instance, are used to stipulate the end of the code. On the other hand, the entity section presents the name of the design including all outputs and inputs to be used in the integrated circuit. The entity section’s performance uses input and output bits. The code in the entity section is provided in the following manner. Input_1_input_2_input_n:in_bit; Output_1_output_2_output_n:out_bit; entity_name; Entity names begin with letters and can consist of underscore characters and numbers as well. Circuitry_integrated is a valid name and entity code that can be used in an effective VHDL code. The architecture section presents the manner in which the entity named operates its functions (Pedroni, 2005). That is; it presents how the output function is attained from the input section. The code of the arch name is presented in a manner of arch_name of entity_name. The two define the behavior of the integrated circuit behavior in this case. Arch_name is the end of the code with a semicolon in the end. The logic design of the circuit as given above follows a function presented as the following: F (Tr, Ty, Tg) = TrTy + Tr’ TyTg’ + TyTg Thus, the library declaration for the circuitry is library IEEE. Thus, the VHDL code is ieee.std_circutry_1163.all; the code for the entity section is as follows: Library 1_vhdl, which is also the port. The input bits are a, b, and c. In the code, they are represented as Tr, Ty, Tg; The in-bit is then given as and ends with the semicolon. The output port then follows, which is represented by F in the logic design function. That is; f: out-bit; the end of the code is library 1_vhdl The entity section function is to describe the output and inputs, as well as the circuit pins. The architecture section of the logic design provided follows the code provided below. The dataflow of the architecture begins the through the lab 1_vhdl The function (logic design) is then implemented The function is: F = TrTy + Tr’ Ty Tg’ + TyTg The end of dataflow will then end as F Read More