Mechanism of the Defect Formation - Essay Example

SUMMARY OF ARTICLES Li, W., Wang, X., Zhang, X., Zhao, S., Duan, H., & Xue, J. . Mechanism of the Defect Formation in Supported Graphene by Energetic Heavy Ion Irradiation: the Substrate Effect. Scientific reports, 5. This article involves report on systematic study of experiments on ion irradiation on SiO2-supproted graphene and the comparison of the results of the experiment quantitatively with simulations of molecular dynamics. The work reports an organized tentative study of the fault yield (γ) in graphene below active ion emission. Various ion species are applied with huge sort of the ion energy. MD simulations are performed to provide a comparison base for the results of the experiment in order to identify with the fundamental mechanism. The result of this shows to have defect formation depending on nuclear collisions up to attainment of threshold of ~ 2.2 keV/nm by Se over which the electronic energy loss becomes significance. The results from the experiment are given in terms of tables and figures. Figure 1 exhibited a distinctive Raman spectrum evolution of ID/IG in SiO2-supported graphene, in which 1 Mev C ions were applied. Table 1 constitutes a list of experimental results of estimated fault yields. There is calculation involving application of SRIM, the electronic stopping power, Se and the nuclear stopping power Sn of occurrence ion in SiO2 and graphene. Figure 2 involves a plotting graph on fault yields in graphene against irradiated ion in graphene nuclear stopping power. The conclusion shows threshold to be set by SiO2 substrate and also the defects of small size are formed in the graphene that is supported (Wang et al. 2015). Yeom, D. Y., Jeon, W., Tu, N. D. K., Yeo, S. Y., Lee, S. S., Sung, B. J., ... & Kim, H. (2015). High- concentration boron doping of graphene nanoplatelets by simple thermal annealing and their supercapacitive properties. Scientific reports, 5. The article is all about the study which involves demonstration of B-doped graphene nanoplatelets which can be developed by simple thermal annealing of GO nanoplatelets in boron oxide combination. This article begins by an abstract, which introduces us to graphene and its properties that enhance the carrying out of the experiment. Boron-doped graphene is introduced to be having electrical properties that are easily influenced by oxygen and water impurities. The next part is the introduction which discusses all that is in the body of the article. Various temperatures are then provided for thermal annealing of Boron oxide or GO mixture to control boron doping effectiveness systematically and level of GO reduction. The article then covers the results and discussion part. Graphene oxide is obtained by oxidation beginning with graphite exfoliation. Boron-doped graphene nanoplatelets have been prepared through boron oxide aqueous solution formation and Graphene oxide or boron oxide thermal annealing. Figure has also provided BT-rGO preparation. There is quantitative and qualitative characterization of BT-rGO and T-RGO samples at variety of temperature. The synthesis of doped graphene nanoplatelets has shown to remove GO oxygen group with g-boron oxide being decomposed at 1000 degrees Celsius annealing temperature. Calculations are also carried out for O/C area ratios of both T-rGO and BT-rGO for quantitative characterization. Effects of boron doping on the electrical features of BT-rGO is investigated and exhibited. The conclusion ends the paper summarizes all the points discussed in the main body. BT-rGO has been proved to undergo concurrent reduction and GO doping. This process is concluded to be favorable for gram-scale B-doped graphene nanoplatelets production (Yeon et al. 2015). Ieong, M., Doris, B., Kedzierski, J., Rim, K., & Yang, M. (2004). Silicon device scaling to the sub-10-nm regime. Science, 306(5704), 2057-2060. This article involves the discussion of difficulties and solutions for continuous performance trends of silicon device towards sub-10nm gate regimes. The transistors which are smaller in size functions more effective than the larger ones, hence the cost of chip is stated to decrease with area and not the number of transistors. MOSFET (metal oxide semi-conductor field-effect transistor) has been taken to be a principal channel transistor, substrate and doping efficiently providing back-to-back junction diodes. Transistor shrinking involves packing excess devices into a certain area and reduction of source-drain gap. Fabrication and performance maintenance have shown to be causing difficulties in reducing the size of MOSFET. MOSFET has got applications as an electric switch or amplifier. Starting of a MOSFET involves application of threshold voltage, which also determines the leakage current. Reasons for keeping the voltage high are to allow minimization of power consumption when the device is not operating and to promote the right noise margin. Much gate overdrive is needed for high performance of device to allow for faster switching. The best choice for threshold voltage of best performance is dependant on the device’s application. The solutions for device scaling involve development of conventional MOSFETs on substrate of silicon-on-insulator. The insulator creation involves oxygen ion implantation and layer annealing for oxide formation. Ultrathin SOI MOSFET is involved in the efficient reduction of SCE (Short Channel Effect) and leakage paths elimination thus good for device scaling. Faster movement of carriers enhances the performance of device and can be done through strain engineering and orientation effects. Finally, there is the target of production of sub-10-nm gate-length MOSFETs of 5 A oxide thickness and junction length under 10nm by 2016 (Ieong et al 2004). Pan, D. Z., Yang, J. S., Yuan, K., Cho, M., & Ban, Y. (2009, October). Layout optimizations for double patterning lithography. In ASIC, 2009. ASICON09. IEEE 8th International Conference on (pp. 726- 729). IEEE. This article is involved with the discussion on the current achievements to boost decomposability and patterning value in DPL (double patterning lithography). Layout decomposition methods currently developed are surveyed. The layout decomposition is grouped as model-based and rule-based. Rule-based is easier in application as compared to model-based which is expensive. Many pioneers concentrate much on rule-based methods. A practical patterning layer decomposition flows was ones proposed by Kahng et al. Yuan et al. also made ILP based layout decomposition algorithm for instantaneous variance and suture minimization. Yang et al. on the other hand suggested an overlay alert timing examination technique from translation measurement together with rotation and magnification overlay. DPL friendly routing approaches are provided with the layout decomposition referred to be the most crucial step for DPL, however it is more complicated and difficult to solve using 2-colouring algorithm. The recent effort by industries for completion of layout decomposition is through completion of in depth routing the carry out layout decomposition for DPL. The first DPL friendly routing logarithm is brought by Cho et al. this does routing and layout decomposition in one shot, in a right way by construction. It is to allow for completion of elevated layout decomposability, minimizing chances of overlay-error-prune stitches. Layout decomposition is usually done by double patterning friendly OPC to minimize layout decomposition complication and difficulty. Gridded design rule about one dimensional layout is a DPL layout optimization way out. Double patterning has shown to be the top entrant for 22nm lithography way out and possibly 15nm technology node considering EUV accessibility (Pan et al. 2009). Kahng, A. B., Park, C. H., Xu, X., & Yao, H. (2008, November). Layout decomposition for double patterning lithography. In Proceedings of the 2008 IEEE/ACM International conference on Computer-Aided Design (pp. 465-472). IEEE Press. This article addresses the problem of splitting DPL into two parts by application of layout decomposition including node splitting processes, detection of conflict cycle and graph construction. The methods have been analyzed artificially 45nm generated test cases and in actual world. DPL typical approaches are litho-etch-litho-etch (LELE) and self-aligned approaches. LELE approach involves transfer of pattern of the first oppose layer into hard mask beneath while self-aligned involves formation of nitride layers on the patterns’ sidewall. The major issue involving DPL from the design side is the decomposition for various exposure steps. DPL layout decomposition needs to achieve opposite colors assigned to two features if the gaps in below minimum coloring spacing. DPL layout decomposition flow is applied and DPL layout decomposition cast as problem for modification of variance graph by decomposition of chosen layout feature nodes. IPL-based coloring is done after detection of iterative variance cycle and node-splitting procedure to come up with an optimal coloring solution not leaving out the number of cuts. The main difficulty of double patterning in widespread deployment in random sequence circuits is need for design observance with design decomposition and patterning needs. Pattern configurations for which characteristics exists less coloring spacing cannot be given different colors at a whole. Odd-length cycle is identified in the conflict graph for detection of pattern configurations in which non-touching characteristics cannot be given various colors. Node splitting application is also done on nodes in conflict cycle to get graph with no conflict value. The methods, splitting a within the conflict cycle and reporting conflict cycle that cannot be resolved for elimination by layout optimization, are applied by node splitting in handling conflict cycle (Khang et al. 2008). Keum, D. H., Cho, S., Kim, J. H., Choe, D. H., Sung, H. J., Kan, M., ... & Lee, Y. H. (2015). Bandgap opening in few-layered monoclinic MoTe2. Nature Physics.2 This article reports production of single-crystalline MoTe2 showing reversible structural alteration conversion between 2H and IT-MoTe2 and electronic stage conversion semi metallic and semiconducting monoclinic single -crystalline MoTE2. Electrical features of minimum-layered MoTe2 are examined using transport measurements relying on temperature and this has been shown by figure 3. Computed energy hurdle of IT phase is near absorption edge with the 2H phase showing minimum value as compared to optical band gap. IT-MoTe2 metallic behavior shows band gap to exist in various few-layer samples closes as the layers’ numbers raises. The 2H-MoTe2 transport computation gave the ambipolar behavior with t6he highest field-effect mobility ever given in 2H-MoTe2. Shubnikov-de Haas oscillation together with its beating featrure s is seen with specific peak periods of 280T and 26T beating period. Beating presence signifies participation of multiple bands in transportation of carrier. These may be electron, hole or spin bands made through effect of Rashba possibly the beating origin. Balanced raise in conductance with raising temperature shows that both the 2H and IT polymorphous have bag gaps consistence with initial former results of photo-absorption spectroscopy. IT phase lack in MoTe2 is analyzed by impulsive structural deformation from IT-MoTe2 controlled by Fermi surface nesting. The structural distortion has currently been reported to be causing intrinsic band inversion in set 6 monoclinic TMDs. Theoretical computations have also exhibited more electron doping producing more efficient Fermi surface nesting promoting high IT stage instability. Peierls deformation has shown to support IT phase formation but does not always involve bang gap opening (Keum et al. 2015). REFERENCES Kahng, A. B., Park, C. H., Xu, X., & Yao, H. (2008, November). Layout decomposition for double patterning lithography. In Proceedings of the 2008 IEEE/ACM International conference on Computer-Aided Design (pp. 465-472). IEEE Press. Keum, D. H., Cho, S., Kim, J. H., Choe, D. H., Sung, H. J., Kan, M., ... & Lee, Y. H. (2015). Bandgap opening in few-layered monoclinic MoTe2. Nature Physics. Ieong, M., Doris, B., Kedzierski, J., Rim, K., & Yang, M. (2004). Silicon device scaling to the sub-10-nm regime. Science, 306(5704), 2057-2060. Li, W., Wang, X., Zhang, X., Zhao, S., Duan, H., & Xue, J. (2015). Mechanism of the Defect Formation in Supported Graphene by Energetic Heavy Ion Irradiation: the Substrate Effect. Scientific reports, 5. Pan, D. Z., Yang, J. S., Yuan, K., Cho, M., & Ban, Y. (2009, October). Layout optimizations for double patterning lithography. In ASIC, 2009. ASICON09. IEEE 8th International Conference on (pp. 726- 729). IEEE. Yeom, D. Y., Jeon, W., Tu, N. D. K., Yeo, S. Y., Lee, S. S., Sung, B. J., ... & Kim, H. (2015). High- concentration boron doping of graphene nanoplatelets by simple thermal annealing and their supercapacitive properties. Scientific reports, 5. Read More