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High Density Plasma Chemical Vapor Deposition - Assignment Example

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The author starts this paper "High-Density Plasma Chemical Vapor Deposition" with the introduction to the Chemical vapor deposition (CVD) as a chemical phenomenon of material to deposit it on another material. This is done using thin films of different materials…
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High Density Plasma Chemical Vapor Deposition
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?HIGH DENSITY PLASMA CVD I start this article with the introduction to the Chemical vapor deposition (CVD). CVD is a chemical phenomenon of a material to deposit it on another material. This is done using thin films of the different materials. A typical CVD phenomenon includes the exposure of a material commonly in volatile format with the substrate which allows the reaction of those and obtains the desired result, deposit or exposure. During the process byproducts are also produced which are evolved as gas through the chamber of reaction. CVD is the process which is an essential component of various processes which include the powders, coatings, fibers and monolithic materials. CVD is very versatile process which can produce the metallic as well as non-metallic material of any kind. These include silicon, carbon, nitrites, carbides, oxides and also many others. In semi-conductor world, CVT is majorly used in the fabrication process of the semiconductor devices and to the exposure of the amorphous SiO2, Silicon Germanium and tungsten etc. The CVD is also the cause of the production of synthetic diamonds. The major importance of CVD in the industry lies in the fact that this process uses the gases as reactants. So the gas’s properties give much support to the reaction procedures. CVD is far most the best and reliable deposition phenomenon/process present. Its advantages include Versatile in nature – any element can be deposited either metallic or non-metallic About 99.99-99.999% pure results Formation of the material less than the melting point Nearly 100% density Economical There exist various types of Chemical Vapor Deposition. These include Atmospheric pressure CVD (APCVD), Aerosol Assisted CVD (AACVD), Hot Wire (HWCVD), Atomic Layer CVD (ALCVD), Low Pressure CVD (LPCVD), Metal Organic CVD (MOCVD), Plasma Enhanced CVD (PECVD) Rapid Thermal CVD (RTCVD), Remote Plasma Enhanced CVD (RPECVD), Microwave Plasma Assisted CVD (MPACVD) and Ultra High Vacuum CVD (UHVCVD). Introduction to High Density Plasma CVD Now I will start a proper introduction of the High Density Plasma Chemical vapor deposition HDP-CVD). The HDP-CVD process is majorly used for the dielectric gap filling in semiconductor devices manufacturing at very micro level. It is used for the Shallow Trench Isolation (STI) and the dielectrics inter layers in 180-nm, 130-nm and 90-nm technologies. Hope fully it will start for the 65-nm and 45-nm technologies too. Gap fillings at such a small scale are very difficult task. While doing the edge gap filling some factors are also keep in consideration like raising the wafer temperature, plasma density and lowering of the deposition pressure. The reaction chamber is used for the process. Scientists have developed the new generation tools for the higher plasma density. The HDP reaction chamber is included the two sources of the radio frequency (RF). These are coupled with the plasma as inductively and capacitively. Inductive RF controls the plasma density and capacitive RF controls the physical bombardment of ions to the wafers or substrates. The reaction chamber will be discussed in detail later on. HDP-CVD gives improved characteristics for the gap filling in the semiconductor fabrication. A process is explained here as an example. A semiconductor material or substrate is loaded in the reaction process chamber. The high density plasma is generated by the gases including oxygen, silicon, hydrogen and a chemical etching gas which is nitrogen free. This plasma is generated exactly on the substrate semiconductor. After this process the chemical semiconductor substrate is heated to a very high temperature. Normally it ranges from the 550 degree Celsius to 700 degree Celsius. This procedure helps in filling the gap regions without any side effects to the substrate. The layer for filling the gaps is of the silicon oxide. Fabrication Process The process of the high density plasma CVD comprised of the different claims which are as follows The steps which involved in the high density plasma CVD according to the 1st claim are First of all the semiconductor substrate is prepared Second step is to fill that substrate in the process chamber Third step is to get the high density plasma on the semiconductor substrate as well as the layer of silicon oxide. This is done by injecting the oxygen gas, nitrogen free etching gas, hydrogen gas and silicon source gas in the process or reaction chamber. 4th step includes of injecting the secondary main gases in the reaction chamber which include all the gases described above and as well as helium gas. The third main gases which include oxygen, Hydrogen and silicon source gas are injected in the reaction chamber in the 5th step. This is done right after the injection of second main gases. While this substrate is heated up to 550 degree Celsius to 700 degree Celsius. The 2nd claim is to produce the high density plasma in HDP-CVD process by adding a plasma powder to an induction coil which is present outside the chamber. When the first main gasses are added to the substrate inside the chamber as discussed earlier, the outside bias power is applied. One thing must be kept in mind that the plasma powder should be in the range of 2500 watts to 5000 watts. Also bias power should have the rating of about 800 to 4000 watts. There is one thing more about the claim that is discussed firstly. Some of the pre gases are also injected in the reaction chamber prior to the first main gases. These starting gases include silicon oxygen and helium gas. Silicon source gas is actually the silane gas (SiH4) or disilane gas (Si2H6). The nitrogen free chemical etching gas is silicon fluoride gas (SiF4). There is a block diagram representing the whole process Figure: 1. Source: http://www.freepatentsonline.com/6802944-0-large.jpg Preface The process which has been the primary part of the discussion is fully related to the construction and development of a semiconductor device and majorly for the gap fillings in various semiconductor devices. As the development is taking place so rapidly so the semiconductor devices are becoming more sophisticated. The methods used in the manufacturing of different layers of the semiconductor devices is so much integrated that the gap between the adjacent layers are very much reduced. It increases the stability and performance of the devices. These gaps must be insulated with some material and it is quite a hectic task due to reduction in size of the gaps. Low pressure CVD was practiced to fill these gaps with the help of interlayer insulation. This process has some limitations due to the high aspect ratio because the area has been reduced between the two interconnected surfaces of the semiconductor material. That is why the high density plasma CVD is proposed which overruled the LPCVD and become the main processor of the fabrication of semiconductor devices. Device Fabrication There are some lines for the methods used for the fabrication of semiconductor devices. The semiconductor devices are manufactured in this format. It has the first connection and second connection region and the volume between these regions known as semiconductor volume that is arranged as per the requirement. The anode region is adjoined with the first connection region, and the second connection region is associated with the semiconductor volume. The doping is done in relation with the first and second connection regions as well as the semiconductor volume. The fabrication of the semiconductor device claims to have the following steps Inter insulating layer forms a nitride layer on itself Nitride layer (200-800 Angstrom) is then covered with the layer of photo resistant (2500-2800 Angstrom) Developing the photo resist patterns on photo resist layer Photo resist layer must have the thickness as comparable with the thickness and etch rate (selectively dissolve the surface of semiconductor with a solvent) of the interlayer insulating layer. Having photo resist pattern as mask, etch the nitride layer. Interlayer insulation is etched with the photo resist pattern Photo resist pattern is removed then by etching The selection of photo resist materials and the doping is varied in construction of different types of semiconductor devices. Examples are BJT’s, FET’s and other transistors etc. The integrated circuits or precisely semiconductor devices are built on the silicon wafer and on this substrate there are plenty of transistors and other electronic devices present. The components are deposited on the substrate by the special wiring called interconnects. The main layer of the substrate is made of Aluminum and the other secondary layers for depositing other components are then deposited on the base layer. This helps in easy electrical conductivity. Some of the deposition processes are HDP-CVD, Plasma Enhanced CVD and CVD Tungsten etc. The fig of Field Effect Transistor (FET) fabrication is shown below Figure: 2. Source: http://secs.ceas.uc.edu/~kroenker/Teaching/Teaching%20Web%20files/697/697%20Intro%20page_files/image006.jpg The Process Reaction Chamber (High Density Plasma CVD) It is important here to take a glance of the process chamber which is primary key to the HDP-CVD. These chambers are designed to have the ease for the plasma electrons to react with the material for the proper results Figure: 3. Source: http://www.azonano.com/images/Article_Images/ImageForArticle_2740(3).jpg The chamber consists of a bottom, side wall and a dome which is present at the top on the side wall. The dome top gives the chamber diameter. The top and side RF coils are present on the top of the dome and on the side wall respectively. Both coils are separated from each other by a separation. The ratio of coil separation to the diameter of chamber is important and it precisely should be 0.2 – 0.25. Silane Chemistry As it was discussed earlier that Silane SiH4 has been the important product in the deposition process of HDP. Another product TEOS was being tried in place of the silane but no significant results was taken. For the oxidant, the mixture of oxygen and argon is added but this mixture causes the silane to deform at even low temperature. So it has seen that in the absence of oxygen, we get the amorphous silicon film ready to be deposited. This is rather pure one. The flexible and hydrogen free silicon dioxide layer is achieved with proper and careful gas mixtures. This is essential for the pure and right fabrication. The moderate rate must be achieved because the excess of silane results in SiH and excess of oxygen results in SiOH in the thin films of the substrate. Sometimes for getting the moisture-gattering properties, we use silicon rich films. To get more amorphous and hard silicon films, the hydrogen which is in excess must be reduced. This is done by increasing the substrate temperature and increase in the ion bombarding flux in the chamber. Desired results are taken with the desired formatting. The silicon wafers that are primarily used for the purpose of fabrication are made up of pure silicon crystal and the slices are 0.75mm thick. The dopants are used with the silica (SiO2) to process the crystals with chemical vapor deposition. Some Applications of HDP-CVD The applications of HDP-CVD include the high aspect ratio gap filling. The process includes the excitation of the gas mixture which results in the birth of plasma including High density plasma chemical vapor deposition allows getting gap filling of high aspect ratio devices in high quality dielectric films. This technology allows us to get void-free gap filling Solutions regarding the logic applications and advanced memory handling. Some applications include Shallow Trench Isolation (STI), Inter level Dielectric (ILD), and Pre-metal dielectric (PMD). Conclusion A low temperature requirement for the substrate deposition is really considered while working with the high density plasma CVD. So where low temperature is the requirement, oxides are used with the RF bias to increase the ion bombardment energy to get the desired deposition and filling. REFERENCES: 1. (2006). Chemical Vapor Deposition (CVD). Retrieved from http://www.engineershandbook.com/MfgMethods/cvd.htm 2. Ip.com. (2005). Method for a Chuck in a High- Density Plasma CVD Chamber. Retrieved from http://ip.com/IPCOM/000042253 3. Michael, T. (2003). High Density Plasma Chemical Vapor Deposition Process. Retrieved from http://www.patents.com/us-7109132.html 4. FreshPatents.com. (2011). Semiconductor Device and Fabrication Method. Retrieved from http://www.freshpatents.com/-dt20111110ptan20110275202.php 5. FindThat Patent. Methods for Fabricating a Semiconductor Device with etch End Point Detection. Retrieved from http://www.findthatpatent.com/Methods_for_fabricating_a_semiconductor_device_with_etch_end_point,7183218.html 6. Novellus. Semiconductor Manufacturing Process Technologies: Novellus Products and Applications. Retrieved from http://www.novellus.com/products/process_technologies/ 7. FreshPatents.com. High Density Plasma cvd Chamber. Retrieved from http://www.freshpatents.com/High-density-plasma-cvd-chamber-dt20060831ptan20060191478.php 8. Time Domain, CVD, Inc. High Density Plasma Deposition of SiO2. Retrieved from http://www.timedomaincvd.com/CVD_Fundamentals/films/HDP_SiO2.html 9. Articleworld.org. Semiconductor Device Fabrication. Retrieved from http://www.articleworld.org/index.php/Semiconductor_device_fabrication 10. Dobkin, D. High Density Plasma Deposition of SiO2. Retrieved from http://www.enigmatic-consulting.com/semiconductor_processing/CVD_Fundamentals/films/HDP_SiO2.html 11. Applied Materials. Semiconductor: Centura Ultima HDP- CVD. Retrieved from http://appliedmaterials.com/technologies/library/centura-ultima-hdp-cvd 12. Figure: 1. Retrieved from http://www.freepatentsonline.com/6802944-0-large.jpg 13. Figure: 2. Retrieved from http://secs.ceas.uc.edu/~kroenker/Teaching/Teaching%20Web%20files/697/697%20Intro%20page_files/image006.jpg 14. Figure: 3. Retrieved from http://www.azonano.com/images/Article_Images/ImageForArticle_2740(3).jpg Read More
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