Retro Lunar Lander Game - Report Example

Retro Lunar Lander game Student’s Name Project Department of ----- Name of University 2014 Abstract The objective of this paper was to design the processor that controlled the Apollo Lunar landing module the design and development of the processor used a single VHDL processor that was able to perform logical and arithmetic for controlling lunar landing. This reproduction of the old processor of Apollo required assembler software for the project. The processor was able to perform a number of operations which enabled Lunar landing in the moon it as the ability to perform navigation as well as landing. Control systems for Apollo Lunar Lander are usually complex because of functionality required from them, the more complex controls become. The primary manner in which to overcome the amount of control design required is to allow Lunar Lander to complete tasks automatically. Table of Contents Abstract 2 Introduction 4 Design process 5 Design verification 7 VHDL models 9 Input –output 12 Designed model 12 Results 24 Conclusion 25 References 27 Introduction The main focus of this paper is to develop and design a replicate Apollo Lunar landing module processor for Retro Lunar Lander game. This is digital design that is has the ability to perform all functions of the Apollo processor such as landing, measure the altitude of the terrain, measure the velocity and help in landing. The processor that is being designed should be able to carry out this activity this purposes. The digital Lunar landing processor system has particularly developed thanks to many attempts at automation and improvement in efficiency. The fundamentals of Retro lunar Lander game are explained in processor dynamics but the improvements in controls are best understood from system improvement. The Apollo control system was therefore developed from the most basic hydro-mechanical systems that took into account the weight and complexity challenges in Rocket development. The use of VHDL and assembler and programming logic devices are necessary for the implementation. VHDL and assembler will help in prototyping hardware debug functionality module bus interfaces In the system test and maintenance bus will be provided on a card of the processor. This card will be developed using VHDL. The peripheral chipset of Lunar landing module processor card were also developed using VHDL. The block of the system was simulated using board schematics. The current digital software and hardware were used in the design to fit the design of Lunar landing module processor. The connections of the models were developed in a way that signals were able to duplicate. Essentially, this allows the system converts all movements of the Lunar landing module processor into electronic signals that are then transmitted to the control panel through wires. At every control surface of the system are actuators whose movements are determined by control computers. This provides the desire response. There is also the possibility of sending automatic signals originated from the Lunar landing module computers to perform some functions. These systems assist in stabilizing the landing automatically. Design process The design is an important component of in designing Lunar landing game. It involves understanding how the intended purpose of Retro lunar Lander game that is about to be designed thereby allowing the designer to understand what should be incorporated in the processor at the design stage. One of the aspects that the design component has to consider for successful design of Lunar Lander game from the old Apollo Lunar landing module processor. The design process used for lunar Lander is modification of Apollo Lunar landing module processor to support the gaming. The design process used for implementing and verifying Retro lunar Lander game design is as shown in figure 1. Assembler software was employed for schematic block and simulation. Figure 1: design process The Redundancy Component and debugging: The redundancy component in designing a Lunar landing game is a technique whose aim is to get rid of single points of failures within the game. Single point failures refer to a condition that breaks the entire system following the failure of only one device or design element. The Tools Component: hardware required for designing include sockets, wire-wrap wire PCB’s, IC’s, capacitors, resistors, copper wire and IDE ribbon cables. Circuit Boards for prototyping were also required. There are 4 boards that were used in this design that had display drivers, buffers for the interfaces, counter logic; Sockets for 3 IDE interface cables to external modules are visible at the bottom. There are two types of hypervisors: the microkernel and the monolithic. A monolithic hypervisor is a fairly thick layer between the hardware and the guest operating system. These usually carry their own hardware drivers which are different from the drivers found in the guest operating systems. The hypervisors function is to control the access of the guest operating system to memory, processors, input/output (I/O) and separates guests from one another. Sine the monolithic hypervisor is considerably large and carries several drivers, it is usually inappropriate since it attacks the surface. It therefore implies that using the monolithic will compromise with the efficiency of the service. This will also compromise with the hypervisor code, other drivers that it loads, the whole physical host and the guests. Rather than compromise with the efficiency of the system and accept unnecessary risks into the system, the processing model will apply the microkernel architecture to develop Hypervisor. This hypervisor will offer basic partitioning ability that leverages virtualization extensions towards the processor. In this case, the Guest operating systems will use their own original drivers. This eliminates the possibility of a risk from the third-party code. In addition, the micro-kernel hypervisor supports more hardware than the monolithic one and thus there’s no need of coming up with different hypervisor drivers. The size of the TCB is significantly minimized when a guest has its own drivers since guests are not routed via the parent partitioning. Modern processors are usually equipped with virtualization extensions that normally allow the hypervisor to be a far much thin layer. Design verification Design verification carries out a number of tests such as interface, functionality and software. It will be good if the designer asks another individual or group to conduct testing of the system. Doing so, it would allow a wider scope of testing scenarios in order to assure that it is own-built. Asking a third party to conduct the testing will make this process less impartial. As the tester, the system requirements should be checked based upon the parameters defined by set of objectives/expectations. Trial transactions should be made in order to check the validity of the system to make sure if it is working properly. Interfaces: This test will be, board-to board, chip-to-chip or subsystem-level interfaces. It is important to develop a solid interface specification early in the design cycle, since multiple designers will be dependent on the same interface. The interface layer within a system framework is responsible for describing the control knowledge within a specific domain. Due to the fact that interfaces are defined at the knowledge level, the manner in which the inference is conducted is not important. Functionality: this type of verification tests the ability of the system to function. This ensures that it hardware is correct in operation. Any malfunction will be debugged as any hardware that is not compatible may not function. Software and software development tools: software is critical to design as they make the system work. The software can valuable in debugging. Compiling, simulation and execution cannot be carried out without debugging. It is also relevant during the selection of specific design choices at the process’ subsystem level and for the determination of the sensitivity of the overall system selection to change in weights and ratings accorded to various architectural alternatives. Functional analysis is the process of identifying the set of inputs, behaviour, and outputs of software. Analysis may involve a description of technical details, calculations, manipulation of date or other specific classification of functionalities that a system is to accomplish. Use cases are used to describe behavioural requirements for system functionality. Generally, functions are expressed in the form of a task that the system must undertake. For instance, “system must do , to produce . So defined, the functions are used to drive the application architecture of a system. The essence of ascertaining software reliability is in the interest of vendors who need confirmation that their customers will utilize them without failures. Software reliability models are therefore used to ascertain this functionality. They provide information about the reliability of software either by predicting the same from design parameters or from test data. Predicting software reliability from design parameters is a kin to ascertaining the level of defect in the software, thus they are referred to as “defect density” models. These models used code characteristics such as through nesting of loops, lines of code, input/outputs, or external references in estimating the degree of defect in software. Models that test software from test data are akin to testing reliability in growth, thus they are referred to as “software reliability growth” models. The models use statistical correlations to find the relationship between known statistical functions and defect detection data. Good correlations are then used to predict software behaviour in the future. Retro Lunar Lander game is designed under several frameworks which include: knowledge-based systems, real time planning, modelling, value-driven reasoning as well as intelligent communication. In addition to landing, these games must show ability to explore, predict and communicate. However, incorporating programming into the processor controls will optimize the activities of the game with minimal external interference. VHDL models Apollo Processing Module The Apollo Lunar landing module processor has 5 subsystems Processing Module external Interface, Arithmetic Logic Unit, Central Register, Interrupt Priority and Priority Counter Processing Module external Interface – acts as interfaces processing module subsystems to external modules which include 40-pin IDE connectors interface to the other CTL, MEM, and IO modules. Figure 2: Apollo Processing Module Arithmetic Logic Unit- it has 16-bit ADDER that performs 1's complement arithmetic and increment the Z register. It has B and C registers, and logic to inclusive OR the contents of the them with the ADDER. The logic function shows the possible inputs that are required to produce the current output. Central Register – it contains four 16-bit “central registers” computational purpose. Interrupt Priority- The original AGC had five vectored interrupts. This recreation implements three of them: RUPT1, also called T3RUPT which is used as general-purpose timer by the AGC WAITLIST software; RUPT3, also called T4RUPT or DSRUPT, which is used to update the DSKY display at regular intervals; and RUPT4, also called KERUPT, which is triggered by a key press from the user's keyboard. The AGC responds to each interrupt by temporarily suspending the current program, executing a short interrupt service routine, and then resuming the interrupted program. Priority Counter- Twenty memory locations in the original AGC functioned as up/down counters. The counters would increment (PINC) or decrement (MINC) in response to external inputs. Increment or decrement was handled by one 12-step subsequence of microinstructions inserted between any two regular instructions. This replica implements 5 of the counters: OVCTR, an overflow counter incremented or decremented by arithmetic overflow during certain instructions; TIME2 and TIME1, the AGC real-time clock; TIME3, a general purpose timer incremented by a 100Hz signal from the SCALER (SCL); and TIME4, a timer used to update the DSKY display. Figure 3: Priority Counter The manner in which a system set can be defined is mathematically as well as by each present variable being assigned a register. Each Registry unit is capable of flexibility because they can accommodate similar variables to particular unit. In order to gain signal on a unit, it does not have to be an exact match on the unit. Unit sets can be manipulated through logic operators such as AND, NOT as well as INTERSECTIO and INVERSE. When two registry sets combine, the resulting set will contain elements from both sets rather than from any one individual set. It is important to remember that when input registers are involved, the joining of sets will result in a switch closures that contains all elements that as well as the maximum or minimum value selected for the particular signals. Input –output Attention must be paid to the fact that a block necessary for a certain function must be capable of carrying out the task that it is designed for so all other connected tasks can also be accomplished. The Retro Lunar Lander game will actually be created by making modifications to Apollo Lunar landing processor. It will need to be compatible with all sub-systems that will assist in the landing functions. When ddesigning all components of the system are connected with one another. The various blocks making up the system must be designed in a manner that makes them cohesive and compatible with the needs of one another. It is critical to ensure that enough power exists in order to power all the blocks in use. It is expedient that an operating system is in control especially during multi-user processing. This is to ensure that concurrent read and write to data within a database remains consistent especially in a multi-access environment. The windows operating system ensures database consistency by the employment of read and write locks on pieces of data in a multi user-multiprocessing environment. This is necessary in order to prevent deadlock which can affect overall system efficiency. Designed model Generally, a processor can be described as a mathematical model within the context of a lunar landing framework, and is a basic component of any system that is intended to exhibit autonomous behavior in a complex environment. There are a large variety of combinations that processors can be arranged in, but they all have five common characteristics which include: 1. Multiple computer processing elements with each individual one consisting of a local memory. The processors can be implemented at different locations such as the hardware, special chips, as well as within software or parallel computers. 2. Connection lines those are responsible for transmitting information between the processors. Similar to the various locations that the processors can be implemented at, the lines of hardware can also be implemented in different locations. 3. Although a single processor is capable of receiving multiple inputs from mother processors, it can only have a single output leading to other processors. 4. The processor output can take on any type of mathematical form depending on its input. 5. Modifying the memory of the processors so it can be adapted to the environment. Given the fact that neural networks are non-linear and flexible, they can be adapted to and used within various activities such as prediction and forecasting, system identification, classification, optimization and decision support. The following block diagram Figure 4: Block diagram The set up uses a logic and arithmetic unit process controller, which uses a self contained process of signal simulation with an inbuilt controller function, as carried out by Apollo Lunar landing processor. The logic and arithmetic units are connected to MUX, signal is send to induce ALU shift on the shift and rotate block, thus a signal is to convert the electrical power to activate landing. The justifications for this control process is based on the fact that most if not all game require energy utilization, but of late these have become so expensive that maximum utilization has become a key consideration. There is a need to therefore formulate ways and methods of ensuring such processes attain maximum utilization of the available resources at a controlled approach. Logic unit has its advantages in comparison to other methods because it embraces uncertainty and is used in instances where exact numerical boundaries are unknown. However, in order to be autonomous, Lunar landing system need to be utilized within the confines of a neural game system, genetic algorithm or case based reasoning framework. Apollo Lunar landing system offers the advantages of a knowledge-based system for game development. It offers the unparalleled feature of combining low level learning algorithm which operates on a set of knowledge-based rules. The result of this learning phase can then be transformed back into easily interpretable rules, as opposed to the often unintelligible pattern of synaptic connections. In short, logic unit cannot be utilized alone in terms of Retro lunar Lander game, but must be combined with other techniques. Figure 5: ALU contains the 16-bit ADDER The ALU contains the 16-bit ADDER which performs 1's complement arithmetic, and increments the Z register. Each orange box is a 4-bit parallel adder; collectively, they add 16 bits. The ADDER uses the X, Y, and U Registers(X): the 16-bit extension register that holds one of two inputs To the ADDER; Y: the 16-bit extension register that holds the other input to the ADDER. U: the ADDER output. Outputs to the bus labeled “B” on the diagram. The ALU also contains the B and C registers: B: a general-purpose buffer register also used to pre-fetch the next instruction. At the start of the next instruction sequence, the upper bits of B are copied to the SQ register, and the lower bits are copied to the S register in. Output to the bus labelled “A” on the diagram. C: not a separate register, but the 1's complement of B. Figure 6: Therefore, the basic principle of operation in the binary is the decomposition of a single point time domain signal into two t time domain signals that each contains a single point. What follows this initial decomposition stage is the calculation of the frequency spectra that corresponds to the given t time domain signals. The final stage involves the synthesizing of the calculated t spectra into a single frequency spectrum. A given a typical 16 point signal, it can be decomposed through four stages that are each distinct. The first stage of decomposition results in two signals that each has 8 points while the second stage of decomposition will result in four signals that each has 4 points. The idea is to continue this decomposition by half until a given number of signals, in this case 16, that each contains a single point remain. It should be noted that each decomposition stage is interlaced in nature and this means that the two samples which result from a decomposition are even and odd numbered respectively. An important feature to note concerning the decomposition process is that it is what makes it possible for the samples in the original signal to be reordered. However, the re-ordering of these samples is supposed to follow a specific pattern which is determined by the binary equivalents of each sample. After the bit reversal sorting stage of the algorithm, the next step is the finding of the frequency spectra which belongs to the 1 point time domain signals at the end of the last decomposition phase. This is a very easy process since the frequency spectrum of a 1 point signals is equal to itself and therefore there is virtually nothing to be done at this stage. Also, it should be noted that the final 1 point signals are no longer time domain signals but rather, a frequency spectrum. Lastly, the frequency spectra are then supposed to be recombined in the reverse order that is exactly similar to the order followed during the decomposition of the time domain. Since bit reversal formula is not applicable for this recombination, the reverse process is performed one stage at a time. The reverse process is known as synthesis and this is done stage wise from the single point spectra and finally forming the 16 point frequency spectrum. The different flow diagrams used to represent this synthesis is referred to as a butterfly and it is also what forms the basic computational element of the binary as it transforms two complex points into two different but still complex points. The process of synthesizing the frequency domain from the separate single signals undergoes three main essential loops which are also concentric in nature. The outermost loop is the one that runs through the Log2N stages while the middle loop is the one which moves through each of the individual frequency spectra that are in the stage currently being worked on. The final loop which is also the innermost is what now uses the butterfly diagram mentioned earlier in the calculation of the points that are in each frequency spectra. The three loops are the three main stages that constitute the transformation of a given data from the time domain data into the frequency domain data and vice versa. Figure 7: bits Due to their ability to generalize, these systems are better suited for control applications than traditional controls. As well, since they are highly parallel, they can easily process large quantities of sensory information. There are four primary reasons why artificial neural networks are well suited within the control system of a lunar Lander. They include: 1. Since networks provide a link between sensors and motors, they are well equipped to handle a constant flow of input and output signals. 2. They can adapt to noisy environments given the fact that their units are constructed based on several weighted signals. The changes in the individual values of the signals do not impact the behavior of the entire network. 3. Networks can be adapted to an array of learning algorithms. 4. Networks are flexible so learning techniques can be applied to various levels within the neural network. Depending on what needs to be achieved board can be arranged in different architectures. Feed forward arrangement is the simplest example of system. They are described as network connections whose units do not form a full circle. Information flows in a singular direction from the input layer to the output layer. What happens within the input layer is representative of what occurs within the individual networks. Every neuron which is put into the system is directly connected to a variable that controls the output. The functions that can be carried out by a network depend largely on its topology as well as the transfer function of its layers. Functions which are nonlinear are customarily made up of a singular layer of nodes which are hidden as well as an output layer which is linear. The following sections will examine various designed lunar landing module processor which is a replica of Apollo lunar Lander is made by a register transfer level of VHDL coding. The diagram below shows internal interconnections for the subsystems in the PROC module. Figure 8: control bus The PROC module External Interfaces to the CTL, MEM, and IO modules through 40-pin IDE ribbon Cables PROC CONTROL PANEL PUSHBUTTONS Figure 9: Process control RUPT1 Set the RUPT1 flip-flop (FF). Simulates a TIME3 overflow. Triggers a T3RUPT. RUPT3 Set the RUPT3 flip-flop (FF). Simulates a TIME4 overflow. Triggers a T4RUPT (DSRUPT). RUPT4 Set the RUPT4 flip-flop (FF). Simulates a DSKY key press. Triggers a KEYRUPT. TIME1 Set the TIME1 flip-flop (FF). Increments the low-order word of the AGC real-time clock. TIME2 Set the TIME2 flip-flop (FF). Increments the high-order word of the AGC real-time-clock. TIME3 Set the TIME3 flip-flop (FF). Increments the general purpose timer. TIME4 Set the TIME4 flip-flop (FF). Increments the display update timer. In this case, in control bus diagram 1 the signal is placed across the AGC process control Within process control, each input that is received from the specified environment is in association with a specific design. During this procedure, the weights are assessed on a periodic basis throughout the learning process until the system is optimized. This method is applicable in cases where the programmer knows the needed output of the system in relation to the input patterns. Once a network has established the correct output patterns based on what is input, it can also produce correct output responses for new data. The most common manner in which to have a hypothesis space that is inclusive of all representations and is predictive of future outcomes can be achieved by considering the best hypothesis should be chosen and weighted against a better measurement. PROC INDICATORS The PROC module has a panel of indicator to show the state of PROC registers and critical logic signals. These indicator lamps show the current state of all registers and some additional, important logic signals produced by the PROC module. AGC numbers are represented in octal, so all register lamps are in groups of three. At the time the photo was taken the AGC was running the COLOSSUS 249 flight software load, executing Verb 16, Noun 36: a monitor verb which displays the AGC real time clock. At the start of the code shown, analogy inputs are assigned to the input 1. The red indicators plugged into processing assembly card corresponding to the game is then coded to give a digital output of LED off when the corresponding input is below a certain value and 1 LED on when the corresponding input voltage is above a certain value. The response is accepted to have lights red that is red and the other yellow. When the red light is shown it means the temperature is declaring and it requires digital activation for the signal to increase so that the game will be played. When the LED is red and above yellow light is shown. This means the red light will act as an input while the yellow acts as output light. The digital control system is a complete makeover of the Apollo Lunar Lander operations. In this system, signal processing is undertaken through a digital computer. The flexibility of the Retro lunar Lander game is improved tremendously because the computer is capacitated to receive signals from a myriad of modules. The digital system also increases electronic stability since the control system depends less on the input values of critical signals components as it happens in the Apollo Lunar Lander systems. Once the computer has sensed force inputs and positions from sensors, they manipulate a series of differential equations to determine which of the command signals is appropriate to best execute the game. Results The operation of a Lunar landing module processor works on a relatively simple command- a simple feedback loop that, in reality, is quite complex. The figure below illustrates the simple feedback loop command of a Lunar landing module processor. When the player moves the control column, a signal is transmitted to a computer through a number of channels. This is to ensure that the signal is received by the computer. A triplex channel, for instance, includes three such channels. After the computer receives the signal, it performs a number of calculations chief of which involves adding signal voltages, before dividing them by the number of channels received. This gives he average signal voltage. Another channel is then added to the three signals, and the four signals then sent to the actuator on the control surface. This moves the surface. A series of potentiometers within the actuator then returns a signal to the computer to report the current position of the actuator. This signal is usually a negative signal. When the desired position of the actuator is attained, the outgoing and incoming signals cancel out each other thereby stationing the actuator at its present position. This completes the feedback loop. The automatic stability systems of lunar landing module processor enable the Retro lunar Lander game with only little or no input. Conclusion The effectiveness regarding the proposed technique of replicating Apollo lunar Lander is established through applying the method to both the simulated signals as well as the realistic bearing vibration signals generally under many different conditions. As such, the results do show that such a proposed method can be an effective technique that can be used to determine the lunar Lander game. Significantly, it is vital to consider having the knowledge concerning the advanced methods regarding the Retro lunar Lander game using the old Apollo Lunar Lander processor all the way to the diagnosis. In addition, it is important to consider the vital area like the reliability as well as the technicality of the processes is guaranteed. Following this process, error occurs with similar processes while considering the relationship that does exist between signals like the parameter estimation, observers, component analysis and parity equations. Furthermore, there are several examples that can be considered when it comes to error detecting during debugging as well as the diagnosis of the proc board which are all linked as some applications. As a way of facilitating, the detection regarding the defects that are experienced in the vibrators are normally converted to strong electrical signals with sensors, which are the pre-conditioned therefore converting them to digital signals. Retro lunar Lander game combines with logic and arithmetic units seem to be a better combination than using the two frameworks on an individual basis. This two units are highly valuable and should be utilized because they reduce the amount of time to spend on locating and analyzing data for the game. This seems like a feasible solution because if developed properly, this game can easily adapt to new game and offer developers faster feedback as to the feasibility and potential of improving. As well, utilizing Lunar Lander processor based on genetic algorithms will allow designers to create other games. References Brown,S. & Zvonko,V., 2005. “Fundamentals of digital logic with VHDL Design” 2nd Edition, New York: McGraw Hill International. Dewey, A. 1997. “Analysis and design of digital system with VHDL”, PWS publishing company. Grantner, J. L., Tamayo,P.A., Gottipati,R. & Florida, D., 2005. Development of a Test Bench for VHDL Projects. American Society for Engineering Education Annual Conference & Exposition Han, C., Johnson, M. & Miller, D., 2011. Development of Modular Real-Time Software for the TALARIS Lunar Hopper Testbed McCabe, P., 2010. VHDL-based system simulation and performance management. Honeywell Inc. Space systems. Pultorak, J., 2004. Block I: Apollo Guidance Computer (AGC)- How to build one in your basement. Part 3: Processing (PROC) Module. Retrieved April 09, 2014, from Ramon L. Alonso R. & Hopkins, A., 1963. The Apollo Guidance Computer. Retrieved April 09, 2014, from Zwolinski, M., 2000. “Digital System Design with VHDL”, New York: Prentice Hall. Read More

Figure 1: design process The Redundancy Component and debugging: The redundancy component in designing a Lunar landing game is a technique whose aim is to get rid of single points of failures within the game. Single point failures refer to a condition that breaks the entire system following the failure of only one device or design element. The Tools Component: hardware required for designing include sockets, wire-wrap wire PCB’s, IC’s, capacitors, resistors, copper wire and IDE ribbon cables.

Circuit Boards for prototyping were also required. There are 4 boards that were used in this design that had display drivers, buffers for the interfaces, counter logic; Sockets for 3 IDE interface cables to external modules are visible at the bottom. There are two types of hypervisors: the microkernel and the monolithic. A monolithic hypervisor is a fairly thick layer between the hardware and the guest operating system. These usually carry their own hardware drivers which are different from the drivers found in the guest operating systems.

The hypervisors function is to control the access of the guest operating system to memory, processors, input/output (I/O) and separates guests from one another. Sine the monolithic hypervisor is considerably large and carries several drivers, it is usually inappropriate since it attacks the surface. It therefore implies that using the monolithic will compromise with the efficiency of the service. This will also compromise with the hypervisor code, other drivers that it loads, the whole physical host and the guests.

Rather than compromise with the efficiency of the system and accept unnecessary risks into the system, the processing model will apply the microkernel architecture to develop Hypervisor. This hypervisor will offer basic partitioning ability that leverages virtualization extensions towards the processor. In this case, the Guest operating systems will use their own original drivers. This eliminates the possibility of a risk from the third-party code. In addition, the micro-kernel hypervisor supports more hardware than the monolithic one and thus there’s no need of coming up with different hypervisor drivers.

The size of the TCB is significantly minimized when a guest has its own drivers since guests are not routed via the parent partitioning. Modern processors are usually equipped with virtualization extensions that normally allow the hypervisor to be a far much thin layer. Design verification Design verification carries out a number of tests such as interface, functionality and software. It will be good if the designer asks another individual or group to conduct testing of the system. Doing so, it would allow a wider scope of testing scenarios in order to assure that it is own-built.

Asking a third party to conduct the testing will make this process less impartial. As the tester, the system requirements should be checked based upon the parameters defined by set of objectives/expectations. Trial transactions should be made in order to check the validity of the system to make sure if it is working properly. Interfaces: This test will be, board-to board, chip-to-chip or subsystem-level interfaces. It is important to develop a solid interface specification early in the design cycle, since multiple designers will be dependent on the same interface.

The interface layer within a system framework is responsible for describing the control knowledge within a specific domain. Due to the fact that interfaces are defined at the knowledge level, the manner in which the inference is conducted is not important. Functionality: this type of verification tests the ability of the system to function. This ensures that it hardware is correct in operation. Any malfunction will be debugged as any hardware that is not compatible may not function. Software and software development tools: software is critical to design as they make the system work.

The software can valuable in debugging. Compiling, simulation and execution cannot be carried out without debugging.

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