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Synchronized Access to Shared Memory by Multiple - Essay Example

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A Chip-Level Multiprocessor (CMP) or a Multi-Core Processor has two or more independent CPUs integrated on a single Integrated Circuit (IC). Such an arrangement is useful since it allows two or more different operations to run simultaneously increasing the processing output…
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Synchronized Access to Shared Memory by Multiple
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Download file to see previous pages Various techniques which can be used to achieve this are discussed in the following paper.
A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores (normally a CPU) into a single package composed of a single integrated circuit (IC). The below diagram "Dual CPU Core Chip" (Schmitz, 2004) gives an idea about it.
The principle behind current Multi-Processing (MP) systems is that computations requiring large amount of CPU usage could be broken up into many relatively independent parts. These parts, called threads, while being executed simultaneously, could either be of the same or different process. Since these threads could be inter-dependant, issues of memory architecture and in particular memory consistency and cache behavior are 'key' to both correctness and performance in multi-processing systems.
Multi-Core Processors (CMPs) could be broadly classified as Uniform Memory Access (UMA) processors in which all the CPUs are able to access all the memory with no specific preference or Non-Uniform Memory Access (NUMA) processors, where each CPU may have its own special memory area. A system may maintain memory consistency using hardware or using a combination of hardware and software techniques. Hardware can provide a particular memory ordering guarantee, (hardware will maintain the sequential nature of program memory accesses), while software can be used supplement hardware-provided memory ordering by forcing additional ordering restrictions at desired times. The memory ordering scheme implemented is a design choice involving a tradeoff between hardware complexity, software complexity, and the desired ability to cache and buffer data.
Non-Uniform Memory Access (NUMA) Architecture
Refer Diagram "NUMA Architecture." (Watson, n.d., p. 4) In NUMA architecture a processor can access its own local memory faster than non-local memory that is, memory local to another processor or memory shared between processors. In this type, all the MPs may or may not be of similar capacity (Asymmetric Multi Processing). Communication between processors is often based on use of shared memory between those processors. An 'Inter Process Interrupt' (IPI) allows CPUs to generate notifications to other CPUs to invalidate entries for a shared region or to request termination.
Uniform Memory Access (UMA) Architecture
Refer Diagram "UMA Architecture." (Watson, n.d., p. 3) When multiple processors can access the same shared memory, the MP system has to make sure that the ordering of memory access from one processor is made visible to the other processors.

Memory Fencing
One way to achieve 'Cache Coherence' in a MP environment would be by using 'Fencing' technique. Refer Diagram 'MFDA and MFDR Instruction" (Mittal, 1997, p. 26). In this technique, MP system (11) access and release of shared memory space (15) is done using two special instructions - MFDA and MFDR. The Memory Fence Directional - Acquire (MFDA) (16) instruction locks the specified area from being accessed by other processors. Once the operation is over and data can be released, the Memory Fence Directional - Release (MFDR) (17) instruction is issued. Since an MFDA instruction 'locks' the shared data until its ...Download file to see next pagesRead More
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