Memory Management - Virtual Memory with Paging and Segmentation - Literature review Example

Memory Management Name: Institute: Table of Contents Memory Management 1 Table of Contents 2 1.0 Virtual Memory with Paging  3 1.1 Operating Systems: A Concept-based Approach, 2E 3 1.2 Page Replacement in Distributed Virtual Memory Systems 4 1.3 Characterizing virtual memory write references for efficient page replacement in NAND flash memory 5 1.4 Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table 6 1.5 Performance Measurement and Modeling to Evaluate Various Effects on a Shared Memory Multiprocessor 7 Factors like virtual memory paging, cache coherence, barriers, sequential code, as well as the computer itself with resource multiprogramming along with scheduling stalwartly have an effect on computer’s performance with regards to the shared memory (Zhang, 1991). Zhang presents quite a few timing analyses and models for such effects, and also provides a tailored Ware paradigm rooted in these timing models, which can assess wide-ranging performance of a shared memory computer. In this case, the Encore Multimax system was utilized for measurement of Shared Memory Multiprocessor performance. What’s more, the evaluation paradigms are examinations rooted in a wide-ranging shared memory multiprocessor system as well as structural design, plus they may be utilized to other forms of shared memory multiprocessors. Experimental along with analytical outcomes of the study offer a comprehensible knowledge of the diverse effects as well as an accurate performance measurement, which according to Zhang are imperative for the successful utilization of a shared memory multiprocessor. Every multiprocessor use the straightforward concept: a task can be portioned into a number of subtasks that can be carried out autonomously. Importantly, theoretical examinations of loads of parallel algorithms forecast that speedup heightens with the amount of processors, particularly when the multiprocessor is used to execute the algorithms. Still, bona fide knowledge demonstrates that logically a lot of processors always slow the speedup, for reason such as a number of runtime variations as well as interactions at hand in the multisystem that influences performance are complex to capture in hypothetical examinations. Additionally, this inconsistency is related to the parallel systems and programs effects wherein the algorithms are executed (Zhang, 1991). 8 2.0 Virtual Memory with Segmentation 8 2.1 Computer Architecture and Organization: Design Principles and Applications 9 2.2 Time to split, virtually: expanding virtual publics into vibrant virtual metropolises 10 2.3 Alternate metal virtual ground (AMG)-a new scaling concept for very high-density EPROMs 11 2.4 Access control mechanisms in a distributed, persistent memory system 12 2.5 Application-Controlled Demand Paging for Out-of-Core Visualization 13 References 14 1.0 Virtual Memory with Paging  1.1 Operating Systems: A Concept-based Approach, 2E Memory paging according to Dhamdhere (2006) is a management method for memory for managing how resources of virtual machine's or computer memory are shared. Basically, a PC can address memory above the amount set up on the computer. Dhamdhere affirms that this memory that is nonphysical, commonly regarded as virtual memory, is in fact a hard disk’s portion that is installed to emulate the RAM of the computer. Virtual memory (VM) notion originates from a period when physical memory, was exceedingly costly. Furthermore, the hard disk portion that serves as physical memory is regarded as a page file. In this regard, when a computer is short of RAM; the OS (operating system) will shift the memory pages towards the hard disk of the computer so as to ease up RAM for further processes. Dhamdhere posits that this ascertains that the OS will by no means run short of memory and collapse. However, over dependence on memory paging might damage computer performance, for the reason that RAM operates much quicker as compared to disk memory. This according to reference denotes that the OS has to await the disk to draw near whenever a page is swapped; therefore, when workload over rely on swap files, it will harmfully affect the performance. Importantly, techniques-based on memory paging in a virtual setting consist of: Hypervisor swapping, which offers long-standing support for page swap at the expense of certain portion of memory reclamation. Even though hypervisors usually lack VM memory insight, still the information swapped out probably will regularly require to be re-swapped which according to Dhamdhere can mortify performance. Smart paging is another memory paging approach utilized simply during the virtual memory restart, especially when memory is not accessible plus not a bit can be recovered (Dhamdhere, 2006). 1.2 Page Replacement in Distributed Virtual Memory Systems Malkawi, Knox, and Abaza (1992) introduce page out policies as well as page replacements, in distributed VM systems. Essentially, some of the replacement policies, the global lately applied or brought as well as least lately bestowed, are implemented versions of the policy, least utilized lately which is recognized in traditional VM systems. In the study, Malkawi et al, utilized simulation, which is trace driven to assess the performance of the round robin, replacement policies and least loaded neighbor as well as least active neighbor page out policies. The study outcomes recommend that when internode faults cost is significantly high as compared to local memory access, then remote along with global policies are better than the local one. Furthermore, when the cost incurred for conveying a page from the nearby neighbor is significantly stumpy than the price for gaining entrance to the local memory, then the local policy executes together with the remote as well as the global. Round robin according to Malkawi et al is the least resourceful in the midst of the page out policies and also least loaded neighbor (LLN) generates inferior cost as compared to least active neighbor (LAN) when the local memory size is comparatively enormous. LAN exhibits excellent performance under higher memory strife. In moderately bigger systems, the memory accessible on the system is projected to be adequately enormous to house all spaces of the virtual address, which the processes in tandem deliver in the system. Still, it is probable that the number and size of tasks could heighten to the level where the memory turns out to be flooded. In this regard, the distributed Virtual Memory Systems should make use of the disk space as a virtual space (Malkawi, Knox, & Abaza, 1992). Distributed Virtual Memory Systems uses a technique to settle on when to utilize the disk as a virtual space instead of other nodes the local memories. 1.3 Characterizing virtual memory write references for efficient page replacement in NAND flash memory Lately, according to Lee and Bahn (2009) NAND flash memory has been utilized as the virtual memory’s swap space and also the embedded systems’ file storage. Owing to the dominance of temporal locality in virtual memory’s page references, Lee and Bahn affirm that LRU as well as its estimated algorithms are extensively applied. However, Lee and Bahn study demonstrate that for write references this is far from true. The study examines the attributes of virtual memory write as well as read references independently, where it establishes that the write references temporal locality is feeble and asymmetrical. Rooted in these findings, Lee and Bahn present a novel algorithm for page replacement that utilizes diverse strategies for write and read operations in forecasting the re-reference pages probability. Temporal locality unaccompanied is utilized for read operations, but with regards to write operations, temporal locality along with write frequency is utilized. According to Lee and Bahn, the algorithm divides the memory space into a write area well as a read area to maintain reference patterns track accurately, and afterward their sizes are changed dynamically founded on their I/O costs as well as reference patterns. Although the algorithm lacks exterior parameter to adjust, its performance is more advanced as compared to Clean-First LRU by over 20%. Furthermore, it braces optimized adoptions for VM systems. In this regard, page references in VM setting have a dimension of temporal locality, and therefore the least recently used as well as its estimated CLOCK algorithm are extensively utilized. Still, they fail to weigh the distinct I/O costs of NAND flash memory’s write as well as read operations. Lee and Bahn claim that dirty pages must be flushed to NAND flash memory or swapped out prior to eviction, plus this gains a write I/O that is approximately eight times slower than read I/O. Therefore, a resourceful replacement algorithm must consider these irregular operation overheads. In addition, the temporal locality dimension of VM references must be reexamined when write along with read references are autonomously examined (Lee & Bahn, 2009). 1.4 Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table Zhou and Petrov (2011) present a new page table structure for and memory-constrained as well as real-time embedded system. Scores of high-end embedded processors more and more provide VM support in a structure of paged memory management unit (PMMU), which according to Zhou and Petrov is liable for caching as well as hastily searching for the address mapping needed to access memory. Nonetheless, to entirely put into practice VM support the system software must preserve a page table after every task, whose objective is to capture the virtual data to physical page conversion data for the whole address space. Conventionally, page tables have been developed for universal systems, whereby their real-time performance as well as size was of no primary significance; rather, the page table average performance was the key concern. However, score of embedded systems inflict stringent real-time prerequisites together with constrained memory resources. Therefore, to deal with these challenges, Zhou and Petrov proposes a novel page table structure that not only need considerably less memory as compared to the conventional page tables, but as well facilitates a deterministic page table traversal that is rooted in the hardware. Zhou and Petrov claim that this is attained by taking advantage of application information concerning the memory track of the program being carried out. Loads of high-end embedded systems are progressively developed as multifaceted computing systems carrying out manifold tasks. Therefore, to resourcefully program as well as make use of these hardware platforms, Zhou and Petrov posit that the system capabilities like data sharing, replacement as well as security are required. These features are offered by the virtual memory model that is widely recognized as well-designed method for visible sharing as well as application of hardware resource (Zhou & Petrov, 2011). 1.5 Performance Measurement and Modeling to Evaluate Various Effects on a Shared Memory Multiprocessor Factors like virtual memory paging, cache coherence, barriers, sequential code, as well as the computer itself with resource multiprogramming along with scheduling stalwartly have an effect on computer’s performance with regards to the shared memory (Zhang, 1991). Zhang presents quite a few timing analyses and models for such effects, and also provides a tailored Ware paradigm rooted in these timing models, which can assess wide-ranging performance of a shared memory computer. In this case, the Encore Multimax system was utilized for measurement of Shared Memory Multiprocessor performance. What’s more, the evaluation paradigms are examinations rooted in a wide-ranging shared memory multiprocessor system as well as structural design, plus they may be utilized to other forms of shared memory multiprocessors. Experimental along with analytical outcomes of the study offer a comprehensible knowledge of the diverse effects as well as an accurate performance measurement, which according to Zhang are imperative for the successful utilization of a shared memory multiprocessor. Every multiprocessor use the straightforward concept: a task can be portioned into a number of subtasks that can be carried out autonomously. Importantly, theoretical examinations of loads of parallel algorithms forecast that speedup heightens with the amount of processors, particularly when the multiprocessor is used to execute the algorithms. Still, bona fide knowledge demonstrates that logically a lot of processors always slow the speedup, for reason such as a number of runtime variations as well as interactions at hand in the multisystem that influences performance are complex to capture in hypothetical examinations. Additionally, this inconsistency is related to the parallel systems and programs effects wherein the algorithms are executed (Zhang, 1991). 2.0 Virtual Memory with Segmentation 2.1 Computer Architecture and Organization: Design Principles and Applications According to Govindarajalu (2004), OS can generate manifold virtual address spaces, all beginning at a random location as well as with random length. In this regard, the segment start is virtual address, and all processes could be allocated a distinct segment, and thus, it is entirely oblivious that the memory is shared along with other processes. Replacement is successfully performed briskly at run time by the VM mapping technique. Govindarajalu posit that segmentation is executed in a way much akin to paging, by means of a lookup table. However, the difference is that all descriptors for the segments in the table have the segments’ base address as well as lengths. Normally, segments are restricted to starting on several power-of-two limits that ease implementation of mapping. Govindarajalu posit that a system can inflict a boundary on the segments that are active, as well as their least amount size could be restricted to maximum number of segments of the virtual address. Basically, the utmost number of segments is on average diminutive than the range of the virtual address, so as to maintain the small size of the segment tables. Despite that under lots of conditions, entity processes might be assigned manifold segments, and also a segment descriptor usually conveys several secured data, like the write and read authorization of the segment as well as the Process identifier. In addition, it will have a number of organization data like a presence bit as well modified bit. In the segmentation method, a virtual address is made of a segment offset and segment number. Therefore, if a process contains manifold segments, then it can access a number of the segment number bits, or else the number of the segments is only an identifier allocated by the operating system. Furthermore, in a segmentation plan that is pure the field of segment offset nurtures as well as gets smaller (rationally) relying on the segment length. Therefore, in a archetypal execution, this merely denotes that a number of the high offset order bits are overlooked (Govindarajalu, 2004). 2.2 Time to split, virtually: expanding virtual publics into vibrant virtual metropolises Jones (2000) examines a number of the strong assertions made concerning the importance of virtual memory to e-commerce. The study concentrates on the concept of memory development as a way to develop virtual conurbation, where score of people take part in community computer-mediated discourse. Jones claims that the public approach dejects systemic examination of two-way media systems. By this means, it sidetracks researchers' concern clear of how the content and technology interplay can both allow and constrict the development of a two-way system's user populace along with membership. In this regard, Jone’s paper suggests an optional approach rooted in systems approach. The paradigm generated through this approach concentrates on how to efficiently develop use of and contributions to particular set of computer mediated space, acknowledged as virtual memory. The study recommends that a successful segmentation plan is a vital constituent for those desiring to create a lively virtual memory. In this regard, segmentation strategy according to Jones refers to any logical technique utilized to divide discourse spaces with the intention of generating a system of connected virtual memory. Jones argues that the public viewpoint is not essential in deciding about online groups’ segmentation. Actually, a concentration on public idea could steer business from accurate organization issues into poignant clashes. Whereas memory segmentation based on the public is a usually an arousing subject in the real world, Jones posits that in computer-mediated state of affairs the process seems to be far less challenging. The groups’ segmentation will not automatically have effect upon the community sense, since most of the virtual memory fail to have such a sense concerning them. Splitting groups must be attached to a segmentation plan as well as to the crowding metrics of the virtual memory as they are created (Jones, 2000). 2.3 Alternate metal virtual ground (AMG)-a new scaling concept for very high-density EPROMs Eitan, Kazerounian, and Bergemont (1991) introduces a novel erasable programmable read-only memory (EPROM) collective idea that lessens the size of the cell to the poly pitch in both X-direction boundary regions. The fundamental idea that made the remarkable scaling probable are the quasi-virtual ground array (QVGA) with at least one metal in all two diffused bit lines, the fieldless array, and the segmentation of all other bit line. According to Eitan et al, the for the 64Mb product, the cells required are 2.56 mu m/sup 2/ as well as a 1- mu mm/sup 2/ cell, which is still under development. Such cells according to Eitan et al are smaller by a factor of 2-3 as compared to the normal erasable programmable read-only memory cell, when using the similar technology. The new-fangled array idea as well as its benefits is flexible to flash memories. Notably, the density of EP ROM has been exponentially growing in the past 20 years and doubling-up after 21.5 months. Basically, the EPROM cell scaling drops behind the hasty augment in density, decreasing the area of the cell by a factor of 2 after every three and half years (Eitan, Kazerounian, & Bergemont, 1991). The outcome of the cell as well as density scaling trends is a considerable augment in size of EPROM die for all productions of novel products. Standard EPROM scaling has been executed mostly through shrink design-rule. Novel array structural designs to further decrease the size of the cell was reported by Eitan et al. for instance, the virtual ground approach decreases the size of array by almost forty percent than the standard array of EPROM (Eitan, Kazerounian, & Bergemont, 1991). 2.4 Access control mechanisms in a distributed, persistent memory system Lopriore (2002) presents a distributed, persistent memory system, which executes a type of segmentation attached with paging in a structural design of the single-address-space memory reference model. An irregular quandary of this form of system is the insufficient security of the confidential data objects of any certain process in opposition to illegal access efforts probably executed by the other processes. Lopriore puts forth mechanisms set that can implement access control above the confidential areas of the virtual space. Such mechanisms according to Lopriore assure a level of security akin to that archetypal of a manifold-address-space system, whereas maintaining the benefits of information sharing simplicity, characteristic of the single-address-space paradigm. The ensuing setting is analyzed from several outstanding points of view, which entails ease of revocation as well as distribution of access rights, virtual space reclaim strategies, along with the information storage requirements for management of memory. Lopriore have approached an irregular single address problem of the space systems, that is to say the shortage of any type of information items security in the confidential areas for virtual space of any offered thread from illegal access efforts probably carried out by the other threads, as a result of faults and purposely destructive activities. According to refernce, threads are the dynamic segments equipped to access the inactive pages, segments, as well as entities. On the other hand, processes are an array of strongly attached threads sharing universal pages’ pool. For that reason, Lopriore presents the distributed, persistent memory system in hand with its application program interface that executes segmentation form with paging in the structural design of the single-address-space model (Lopriore, 2002). 2.5 Application-Controlled Demand Paging for Out-of-Core Visualization In the scientific visualization domain, Cox and Ellsworth (1997) afirm that the input data sets are time and again extremely enormous, especially, in computational fluid dynamics visualization. Basically, sets of input data at the moment can exceed 100 GB, plus they are projected to increase with the capability of supercomputers to produce them. A number of visualization paraphernalia have by now portioned enormous sets of data into segments, plus load suitable segments as required. Still, Cox and Ellsworth thinks that this has failed to get rid of the challenge. For reasons such as presence of large entity segments for the main graphics workstations or lots of practitioners lack access to workstations that has enough memory capacity needed to load even one segment, particularly because the up to date visualization paraphernalia tend to be designed by machines that are more powerful. Furthermore, when the data size that have to be accessed is superior as compared to the memory size, a number of form of virtual memory is plainly needed, which maybe through paged segments or by segmentation. Cox and Ellsworth exhibit that entire dependence on OS virtual memory for out-of-core visualization brings about flagrant performance. For this reason, they suggested a paged segment system that can be enforced, plus they investigated the values of memory management, which may be utilized by out-of-core visualization application. Cox and Ellsworth further demonstrate that control of application over a number of can considerably enhance performance. References Cox, M., & Ellsworth, D. (1997). Application-controlled demand paging for out-of-core visualization. Proceedings Visualization '97 (pp. 235 - 244 ). Moffett Field, California: NASA Ames Research Center. Dhamdhere, D. M. (2006). Operating Systems: A Concept-based Approach,2E. Noida : Tata McGraw-Hill Education. Eitan, B., Kazerounian, R., & Bergemont, A. (1991). Alternate metal virtual ground (AMG)-a new scaling concept for very high-density EPROMs. IEEE Electron Device Letters, 12(8), 450 - 452 . Govindarajalu, B. (2004). Computer Architecture and Organization: Design Principles and Applications. Noida: Tata McGraw-Hill Education. Jones, Q. (2000). Time to split, virtually: expanding virtual publics into vibrant virtual metropolises. Proceedings of the 33rd Hawaii International Conference on System Sciences - 2000 (pp. 1-10). Haifa: University of Haifa Mount Carmel. Lee, H., & Bahn, H. (2009). Characterizing virtual memory write references for efficient page replacement in NAND flash memory. MASCOTS '09. IEEE International Symposium on Modeling, Analysis & Simulation of Computer and Telecommunication Systems, (pp. 1 - 10 ). Seoul: Ewha University. Lopriore, L. (2002). Access control mechanisms in a distributed, persistent memory system. IEEE Transactions on Parallel and Distributed Systems, 13(10), 1066 - 1083. Malkawi, M., Knox, D., & Abaza, M. (1992). Page replacement in distributed virtual memory systems . Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing (pp. 394 - 401 ). Wisconsin: University of Wisconsin-Milwaukee. Zhang, X. (1991). Performance Measurement and Modeling to Evaluate Various Effects on a Shared Memory Multiprocessor. IEEE Transactions on Software Engineering, 17(1), 87-93. Zhou, X., & Petrov, P. (2011). Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table. 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