Architecture and Operation of Microprocessors - Research Paper Example

Architecture and Operations of Microprocessors Introduction The process through which raw data is transformed into useful information is known as processing. To carry out this functionality the computer makes use of two elements one is processor and other is memory. Memory is like an electronic pad inside the computer. On the other hand, the processor is like the common sense of a computer in the approach that it systematizes and accomplishes instructions that come from either the user or the software. In a computer a processor generally comprises one or more microprocessors (also known as chips), which are silvers of silicon or other substance stamped with many little electronic circuits. To perform operations on data, the computer passes electricity all the way through circuits to execute an instruction (Norton 2001.p. 5). Task 1 Z80 microprocessor This section will discuss the architecture and principles of operations of Z80 microprocessor. It will also discuss about the main operations, physical and logical structure of the microprocessor. Z80 architecture and principle of operations The Central Processing Units are 4th generation improved micro-proc­essors by excellent application computational strength. Z80 presents highly developed structure output as well as additional well-organized memory operation as compared to 2nd and 3rd generation micro-processors. The domestic program registers hold 2-D-8 bits of rd/write memory that are available to the running programmer. These program registers encompass 2 sets of six GPR (general purpose registers) which can be employed autonomously as moreover &bit CPU registers otherwise while 16bit CPU register pairs. In adding up, there are 2 sets of AR (accumulator register) and FR (flag registers) (Z80, 2009). A group of "Exchange" CPU instructions creates any arrangement of most important or alternating registers presented to the application programmer. The swap set permits processes in forefront setting method or it can be kept for extremely quick break off reaction. There is also a Program Counter, one Refresh register (counter), Stack Pointer, 2 index registers as well as an Interrupt register in Z80. The microprocessor is straightforward to take in into a configuration because it needs merely a sole +5V power resource. The complete production/output signals are completely decoded as well as timed to administer typical memory or secondary circuits; the Z80 microprocessor is holed through a widespread relations of secondary controllers (Z80, 2009). Bock diagram Below I will present the interior block diagram that will show the main utilities of the Z80 microprocessors. Figure 1 Block Diagram of Z80 (Source: http://www.z80.info/zip/z80.pdf) Memory block In the Z80 we have indexing facility for memory. This memory addressing capability that is presented now in the microprocessors was not available in the old microprocessor. In the Z80 indexing ability is used to access blocks memory that contain the data (Fitch et al, 2006). This accessing is carried out in a single instruction. In this on the whole practice an index register will generally hold a dislocation which will be usually further to a base otherwise it could take in a foundation which would be additional to a dislocation. The conclusion of overall discussion is that, we make use of indexing for the memory access in the way of memory blocks (Z80, 2009). Buses Data bus Z80 comprises data bus that is used for input/output, 3-state, active High. Do-De encompasses an 8bit bi-directional data bus, employed for CPU data communications by means of memory and CPU. The address bus is for active High, output, 3-state. The Z80 Address Bus presents the address for data that is stored in the memory at the data bus on connections speed of the equal to 64K bytes as well as for 110 device connections (Z80, 2008). The control bus takes the assortment of CPU synchronization signals necessary through the structure. RAM and ROM In the Z80 we have a random-access memory (RAM) that is write/read memory for the Z80 system. In the Z80 the settings of the control system, the magnitude of random-access memory will normally be little. Conversely, in an application program improvement situation, the quantity of random-access memory will be massive, because it will hold computer application and system programs as well as improvement software. Every content of RAM has to be weighted down previous to apply from an outside device (Fitch et al, 2006). In the Z80 the read-only memory or ROM comprises the computer program proposed for the arrangement. The benefit of the read-only memory is that its filling is enduring as well as performance not vanishes when the arrangement is twisted off. The read-only memory as a result, for all time holds a monitor or bootstrap application or code of a program to allow early Z80 system processes (Z80, 2008). I/O operations This section discusses the Z80 input/output operations. Regardless of different CPU interrupt style position through the user, the Z80 CPU reactions to a mask able disrupts input tracks an extensive timing cycle. Following the CPU interrupt has been noticed through the CPU, an exacting interrupt handing cycle established. This is an unusual Ml (fetch) cycle wherein IORO turns out to be active somewhat than MREQ, because in a usual memory fetch Ml cycle. As well, this particular memory fetch cycle is normally comprehensive all the way through two WAIT conditions, to allow for the instance necessary to recognize the interrupt demand (Fitch et al, 2006). There are two types of interrupt indicators in Z80 microprocessors that are: INT and NMI. In the NMI input interrupt we have a non-maskable interrupt as well as have the greatest preference. The second INT is a lesser preference interrupt as well as it needs that disrupts will be allowed in software with the intention of function. NT can be linked to numerous secondary devices in an agitated OR pattern. In the Z80 we have 1 or additional interface chips consequently to facilitate exchange OF information and data by means of the outside world. The normally employed interface chip is acknowledged as the parallel input/output or PIO chip. This chip directs the major input output functions in the microprocessor (Z80, 2009). Internal registers In this section I will talk about the complete set of registers that are used by the Z80. In the table below I have outlined the main registers for this microprocessor. (Z80, 2008)  Register Size (Bits) A, A' Accumulator 8 F F' Flags 8 B. B' General Purpose 8 C, C' General Purpose 8 D. D' General Purpose 8 E E' General Purpose 8 H, H' General Purpose 8 L, L' General Purpose 8 Interrupt Register 8 R Refresh Register 8 Ix Index Register 16 ly Index Register 16 SP Stack Pointer 16 PC Program Counter 16 IFF7-IFF2 Interrupt Enable Flip-Flops SMFa-IMFb Interrupt Mode Flip-Flaps Instructions Now I will discuss the Z80 instructions which are formatted in 1, 2, 3 or 4 bytes. A Z80 instruction outlines the practice that is to be carried out through the CPU. Starting by means of a fundamental point of view, each instruction may possibly be indicated like an opcode chased through a not obligatory address or literal field, as well as 1 or 2 words. The opcode field states the procedure to be passed out. In stringent computer terms, the op-code stands for simply those bits which identify the process to be carried out, inadequate to the CPU register pointers that can be slotted in (Fitch et al, 2006). The Z80 is prepared by means of additional indexed instructions that require one extra byte. In the setting of the Z-80 the length of op-codes are commonly 1 byte, separately from for exacting Z80 CPU instructions that require a 2-byte op-code (Z80, 2008). A number of Z80 CPU instructions require that single byte of information go after the op-code. In similar scenario, there will 2 bytes in Z80 CPU instruction, the other byte of that instruction is the data (Fitch et al, 2006). In one more instance Z80 CPU instruction could require of a memory address. A memory address has to be 16bits as well as, consequently, 2bytes. In that scenario, the Z80 CPU instruction will force a 3byte or a 4byte Z80 CPU instruction. In the Z80 CPU every byte of the instruction, the CU or the control unit has the duty to carry out a fetch form the memory, which will require 4 clock-cycles. Here we come to the result that is small instruction, the quicker the execution of program (Z80, 2008). Below I have presented the main general scenario of the Z80 instruction. Figure 2 Z80 instruction Source: (Z80, 2008) : www.msxarchive.nl/pub/msx/mirrors/msx2.com/zaks/z80prg02.htm 10 0 010 1 0: 8 bits for the op-code Low address: 8 bits of lower part of the address High address: 8 bits of for the upper part of the address Table source: (Z80, 2008) : www.msxarchive.nl/pub/msx/mirrors/msx2.com/zaks/z80prg02.htm Instruction Set Z80 microprocessor has extra influential and adjustable instruction-sets accessible in several 8bit microprocessors. It comprises unique and distinct procedures because a memory block shifts for quick, well-organized data shifting inside CPU memory, or else inside the memory as well as Input/Output. It as well permits processes on several bits in some places in CPU memory (Z80, 2008). The below given outline of the Z80 microprocessor instruction-set that demonstrates the assembly-language formats , the processes, the flag position, as well as proffers observations on every order. The Z80 microprocessor instructions are alienated into the subsequent groups: (Z80, 2008) 8-bi arithmetic and logic operations &bit loads Exchanges, block transfers, and searches General-purpose arithmetic and CPU control 16-bit loads Bit set, reset, and test operations Calls, returns, and restarts Input and output operation Jumps Rotates and shifts 16-bit arithmetic operations Z80 microprocessor allows the following given addressing modes: (Z80, 2008) Register Register indirect Immediate extended Implied Bit Immediate Relative Modified page zero Extended Indexed Figure 3 Instruction Set Image Source: Source: (Z80, 2009) : http://www.z80.info/zip/z80.pdf Types One word Instruction Two words Instruction Three words Instruction Example Add R1, R2, (25)a; Mul R2, R1, R3 Mov R1, R3 Decoding The Z80 CPU instruction is enclosed in Instruction Register (IR), the CU (control unit) of the C.P.U will decode the inside as well as can produce the right series of internal as well as outside signals intended for the accomplishment of the exacting CPU instruction. There is, consequently, a small decoding holdup trailed through an implementation stage, the span of which relies on the environment of the CPU instruction precise. A number of CPU instructions will carry out entirely within the MPU. Other Z80 CPU instructions will get hold of or place program data opening or concerned with the computer memory. For this reason a lot of instructions of the MPU require an assortment of span of instant to carry out (Z80, 2008). Task 2 A- Conversions No. Decimal Binary Hexadecimal 1 25 11001 19 2 153 10011001 99 3 62 111110 3E 4 230 11100110 E6 5 26 11010 1A 6 208 11010000 D0 7 178 10110010 B2 8 136 10001000 88 9 110 1101110 6E B- Signed Numbers In the microprocessor we symbolize the signed numbers with the help of a particular procedure. The main objective of this section is to look into the main representation of the signed numbers in the microprocessor. Here I will discuss the most commonly used method for this purpose. In this approach we attach a one sign bit to symbolize the sign of the number we are using. This sign bit is generally the most significant bit. In this technique the 0 bit is used for the positive number, and we use 1bit for the negative number (Knuth, 2000). The other set of numbers corresponds to the magnitude or the absolute value of the main figure. Let we have a data of the one byte then in this figure we will have 7 bits of the magnitude or the absolute value and there will be one sign bit (Knuth, 2000). Example is given below: 8 bit signed Binary Signed Unsigned Remarks 00000000 0 0 Positive 00000001 1 1 Positive 01111111 127 127 Positive 10000000 −0 128 Negative 11111111 −127 255 Negative C- Operations (i) 3E AND A2 Binary- 111110 * 10100010 Result- 10111100 Hex Result- 273C (ii) 9B OR 6D Binary-10011011 + 1101101 Result- 100001000 Hex Result- 108 (iii) 7C XOR F0 Binary- 1111100 + (-11110000) Binary- 1111100 + (00001111) Result- 10001011 Hex Result- 8B (iv) CPL 5B Here I will use following conventions 1 for bit forced to be set 0 for bit to preserve Bit masking I will use the OR for the masking of the bits: Binary: 1011011 Force OR to force bits 0, 1, 3, and 5, 6 to be set Bit masking %1100101 %1011011 - - - - - - - 1111111 New value in HEX—7F Task 3 Motorola 6800 vs. Z80 I have selected the Motorola 6800 for comparison with the Z80 microprocessor. No. Motorola 6800 Source: Motorola (1976) Z80 Source: (Z80, 2008) 1. Instruction set contains 78 instructions instruction set contains 158 instructions 2. One index registers Two sixteen-bit index registers 3. 8-bit" 2's complement microprocessor 4. Lese registers More registers 5. Addressing modes: immediate Indexed extended direct Addressing modes: Immediate extended Modified page zero Relative Extended Indexed Register Register indirect implied Bit 6. Has only one bus that is 6800 Bus Data bus Address Bus Control Bus 7. Clocking, Power Ran at 1 MHz Clocking, Power 6.17 MHz 8. The Index register have no facility to directly popped or pushed from the stack Can perform this operation Have no such facility This microprocessor has a subtraction bit in its status flags, for better instruction adjustment References 1. Fitch, J., and Marti, J. January 20, 2006. Nlargeing a Z80 microprocessor, Springer Berlin / Heidelberg, ISBN 978-3-540-11607-3 2. Knuth, D. 2000. The Art of Computer Programming, 2nd Edition: Seminumerical Algorithms, ch- 4.1, page- 136-145. 3. Motorola (1976), Motorola-Annual-Report 1975, page 13, http://www.motorola.com/mot/doc/6/6496_MotDoc.pdf  "We bring in our M6800 C.P.U system" 4. Norton, P. 2001. Introduction to computers, (Fourth Edition), Singapore: McGraw-Hill. 5. Z80, 2008. Hardware Organization, Source: www.msxarchive.nl/pub/msx/mirrors/msx2.com/zaks/z80prg02.htm, retrieved on 11-04-2009. 6. Z80. 2009, Source: http://www.z80.info/zip/z80.pdf, Retrieved on April 13, 2009. Read More