Circuit to Control a Traffic Signal - Assignment Example

Circuit to control a traffic signal Aim: To design and implement a sequential circuit using JK flip flops and control the working of a traffic signalhaving the following characteristics The given clock pulse is of period 10s: a) Green glows for 40s b) Amber glows for 20s c) Red glows for 40s d) Red and Amber glows for 20s Introduction: The given question asks us to implement a circuit for monitoring a traffic signal. Since the application is time dependant, we use a sequential circuit. We design and implement a counter which resets to zero after counting to 11. After designing the counter using the desired flip flop, we design a combinational circuit for the light outputs. Once we connect the counter output values to the traffic light sequence, we get the desired, complete circuit. For solving the given problem, we use a synchronous sequential circuit. In synchronous sequential logic, there is a clock signal, the internal state changes only on a clock edge. The basic storage element in a sequential logic is called the flip-flop. The primary advantage of synchronous logic is its simplicity. Also, the hardware required in sequential circuits is considerably lesser when compared to a combinational circuit undertaking the same task. Synchronous logic also has two main disadvantages: 1. The clock pulse should be distributed to every flip-flop in the circuit. Since the clock is usually a high-frequency signal, this arrangement consumes large amounts of power and dissipates considerable amounts of heat. Even the flip-flops that are not involved in the current operation consume a small amount of power, thereby dissipating heat in the chip. 2. The maximum possible clock frequency is determined by the slowest logic path in the circuit (critical path). To design such a circuit, We undertake the following steps 1) Form a state table showing present state, next state and excitation needed. 2) Decide on the hardware required( JKFF for this question), and compute the JK excitations. 3) Simplify the JK inputs obtained using karnaugh maps 4) Form the circuit from the equations obtained. To design the circuit for the light outputs, we draw a truth table showing the times at which the green, amber and red lights are turned ON. The individual flip flop outputs of the counter are used to denote the variation in time. We then simplify the obtained equation using the karnaugh maps, and hence obtain the final circuit. Theory: JK Flip Flop: The flip flop is an edge triggered device. Its working and characteristics is similar to that of an RS flip flop, but the feedback lines provided ensure that the 1, 1 uncertainty condition of the RS flip flop is avoided. The input 1, 1 operates the JKFF in toggle mode. The 7476 IC is a dual JKFF. It is positive edge triggered. Information is loaded on to the master when the clock pulse is high, and transferred to the slave during transition of the clock state. IC 74LS76 is a negative edge triggered JKFF. The SET and RESET inputs are active low asynchronous terminals. They are used to bring the FF to a desired state, irrespective of the clock and the JK values. The characteristic equation of a JK flip flop is: Counters: Synchronous counters are used to count binary sequences using minimum hardware. They can be designed using any type of flip flop. The number up to which the circuit can count depends on the number of flip flops used. A counter can count from 0 to 2n-1, where n is the number of flip flops used. Extra numbers can be in the counting sequence can be avoided by using proper hardware. The states that are not being used are considered as don’t care conditions when the truth table is constructed. Hardware used: IC 7408(Quad 2 input AND gate): IC 7411(Triple 3 input AND gate): IC 7432 (Quad 2 input OR gate): IC 7476 (JK flip flop) Design: For designing the counter which resets after 11: A truth table containing the present state of a flip flop, next state, and excitation flip flop is drawn. The J,K excitation values are obtained from the present and next states and the characteristic table of JK flip flops The obtained J, K values of each flip flop is then simplified using Karnaugh maps. A circuit can now be constructed using four J K flip flops, and corresponding AND, OR gates. The connections are given to the IC’s according to the circuit diagram. The truth tables for the given conditions are drawn (amber, green, red) with the varying condition as time. By considering the individual flip flop outputs of the counter as denoting the increase in time, the functions for the traffic lights are obtained in terms of the flip flop outputs. These functions are then simplified using karnaugh maps. The output is checked and verified by connecting the input clock to a 100 mHz signal Present State Next State Change A B C D A* B* C* D* Xa Xb Xc Xd 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 1 1 1 0 0 X X X X X X X X 1 1 0 1 X X X X X X X X 1 1 1 0 X X X X X X X X 1 1 1 1 X X X X X X X X Table showing the current and next states and the J, K values (obtained from JK excitation table) Q(a) Q(b) Q(c) Q(d) Green Amber Red 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 Truth Table for Green, Amber and Red output signals KARNAUGH MAPS FOR JK EXCITATIONS: Xa= A.B.C.D + A.C.D Xb= A.B.C.D + B.C.D Ja= B.C.D Jb= A.C.D Ka= C.D Kb= C.D Xc= C.D + C.D Xd= C.D +D + C.D Jc= D = D + D Kc= D Jd = Kd = 1 Circuit Diagram : Counter Using JK Flip Flops Counter that counts to 11 and then resets to 0 KARNAUGH MAPS FOR OUTPUT FUNCTIONS (RED, GREEN, AMBER): Green= A . B Amber= B.C + A.C Red=A +B.C Circuit diagram Traffic Control Signal: Result and Conclusion: The given problem is solved using sequential logic analysis techniques. The circuit obtained gives the required output when a signal of frequency 100 mHz is given at the input. The sequential logic is used since the application is a mainly a function of time. Flip flops are memory elements which can be used to store data, create delays, construct counters, registers etc. By applying the designed counter in combination with a combinational circuit that controls the traffic light signals, we are able to construct the desired circuit. The assignment helps us to understand and implement flip flops and combinational circuits in practical applications. It further helps us understand the basic steps required in designing any synchronous sequential circuit. References: Mano, Morris. M and Ciletti, Michael, D. Digital Design. 4th Ed. 2006 Floyd, Thomas. L. Digital Fundamentals, 10th Ed. 2008. elektropage.com, 2005, 74xx series TTL integrated Circuits Pin diagrams index, accessed on12th November 2008 from http://www.elektropage.com/ic/74xxpin.asp?id=7 Read More