Design of a Motor Speed Sampling, Amplification, Filtering and Display Circuit - Coursework Example

Faculty of Technology and Environment work Design of a Motor Speed Sampling, Amplification, Filtering and Display Circuit Module Analogue and Digital Electronics Module Code: 4004ELE Maximum mark available: 100 Lecturer: Wei Zhang, Mo Ahmed Hand-out Date: 05 February 2015 Hand-in Date: 04 May 2015 Hand-in Method: via Blackboard Feedback Date: 25 may 2015 Feedback Method: via Blackboard Programmes: Beng (Hons) Electrical & Electronic Engineering Meng (Hons) Electrical & Electronic Engineering 1. Introduction This project involves a design of the circuits for motor speed sampling, filtering, amplification and display. It also involves the design of analogue and digital circuit design for conversion from digital to analogue and vice versa as well as the optimization of the output signals. The current amplifier circuit built uses a low-pass filter to implement and simulate a 7 - segment display decoder. The circuit uses a dual a 7 - segment LED display for showing a digital output and switches for generating digital input. In this circuit, diodes and transistors are used for design of simple amplifier and design of circuits to process analogue signal. The design of electronics circuit makes up a combinational digital circuit that will be applied in the sequential logics. The circuit converts a DC current signal of between 2.5 and 2.5mA to a Direct Current voltage signal of between 2V to 3V and uses a low pass filter for suppressing the AC signals whose frequency is above the 100Hz. In the Digital to Analog Conversion, we use an 8-bit DAC for converting the output to a digital signal of 8-bits, which goes through the 4 to 7 decoder. This displays the 8-bit digital signal in 2-bit hexadecimal form on the 7-segment digital display. Part 1: Design a current sampling, amplification and filtering circuit. 1.1. Current sampling/amplification circuit: [10%] The signal outputs of the pulse width modulator on the Current sampling/amplification circuit are varied cycle square waves whose amplitude is 3.3 volts. The signals are both decomposed to form a DC component and a corresponding square wave with amplitude of 0. The concept of generating the DAC output from the pulse modulated signal demonstrates the filter bandwidth by calculating and simulating the analog low-pass filter output to eliminate the high frequency elements and leaves only the DC elements. The low-pass filter bandwidth fundamentally determines the actual DAC signal bandwidth. A source of AC current is used with a frequency of 0.01Hz to demonstrate the slowly transformed output signal of DC current from the motor speed sensor remotely located. 1.1.1. The Op-amp Circuits Figure 1: Circuit Design of an Inverting Amplifier 1.1.2. The Inverting Amplifier The analysis below demonstrates the determination of the output voltage Vo, being a function of the input voltage Vi. Connecting the non-inverting input to the earth makes the virtual ground voltage v+ = 0. From calculations, v- = 0. The assumption is that the current runs towards the ground. The figure 2 below shows the design of the current sampling / amplification circuit. Figure 2: Design of Current Sampling/Amplification Circuit 1.1.3. Demonstration of the gain Demonstration by calculation gives an error source as the peak-to-peak ripple developed by the unfiltered harmonics. The error sources together with other factors yield the overall uncertainty as demonstrated in the equation 1 shown below: TU = Hr = Dcr -----------------EQ1 Where TU = Total Uncertainty, Hr = Harmonic ripples and Dcr = Duty cycle resolution 1.2. Low-pass filter circuit: [10%] The circuit design of the Low pass Filter is demonstrated in figure Figure 3: Design of Low Pass Filter In the actual sense, large resistors, infinite gains and zero-value resistors cannot be designed. The features of the op-amps typically permit the application of the equations that describe the desired op-amp. This is an important factor in the design and analysis of the op-amp circuit. The characteristic input of the op-amp is the resistance Ri in the order of 100MW. It still allows just a little current to enter the input leads. The general output resistance is used as Ro, which is the output of the op-amp, in the order of 10.00W. Since the output resistance is very low, it implies that a non-desired op-amp provides a significant and finite current that derives the approximate values of the voltage output. Equation 2 below approximates the nominal difference of voltage inputs. As the voltage difference becomes larger, the op-amp becomes saturated at the Vsat Voltage (voltage of saturation). The saturation is caused by the voltage difference between the input and output. The input voltage determines what the output voltage Vo will be. Considering the fact that the op-amp does not generate more voltage than that given to it, it reaches an upper limit beyond which it is saturated, and a lower limit below which it saturates. According to Chan and Lim (2008), the Vsat of the op-amp is ever slightly less than the supply voltage, Vcc. For instance, the op-amps applied in this experiment is not able to supply any voltage above +12V and below -12V. The saturation Voltage (Vsat) for the devices is approximately ±10 V. ----------- EQ 2 The characteristic low-frequency gain the open loop of the op-amp is generally 105. Nevertheless, most open amps have an open-loop gains that are frequency dependent and becomes less and according to the input signal frequency. Larger open-loop gains suddenly limit the potential difference between the highest voltage (V+) and the lowest voltage V- (Kleitz, 2002). It also implies that the op-amp is sensitive to minor changes in the values of the potential difference between v+ and v-. It is ideal to avoid saturation and leverage on the sensitive nature of the op-amps. In order to avoid the saturation, we divert a section of the output of the op-amp to the inverting terminal by a physical connection of the output through a passive device to the inversion input. This method is referred to as the negative feedback. It is very a common feature in many suitable op-amp circuits. The function of the negative feedback is to ensure that there is a zero difference between the upper limit of voltage v+ and the lower limit v-. At the same time, it ensures that the op-amp remains sensitive to minor changes in the potential difference between v+ and v-. 1.3. Combined circuit: [10%] Figure 4: Design of Combined Circuit 1.3.1. Graphics and Schematics 1.3.1.1. Low Pass Filter Figure 4 below demonstrates the gain, the Bandwidth and the Rin of the op-amp circuits is demonstrated below through the calculation and simulation. Figure 5: Low Pass Filter The noise comes from the DC current, and it can reduce with the high-pass filter it is amplified. The chopper amplifier makes use of a solid state switch for the input and output to the ground signal appearing at the 0 stage (Brown & Vranesic, 2009). What follows is an input DC voltage of 6-mV and a switch conversion to square wave signal whose amplitude is about 6mV. This is amplified to an AC current of amplitude 6V. In the low pass filter this is shortened to amplitude of 3V. The RC filter acts as a smoothening signal and generates an output signal of about 1.5V dc. 1.3.1.2. Analog Second Order Filters Going to the second order filters, the transition band is reduced to provide higher attenuation of noise. The band pass filter was also made using the second order design. As opposed to the first order filters, the circuits simply needed one extra capacitor. Figure 6: Second Order Low-Pass Filter In the modulation, flicker noises and an amplifier drift often interrupted the amplification of the low frequency signal from the direct current. Modulators are used in the conversion to higher frequency at the point where 1/f is not highly troublesome. Figure 7: Graph of Second Order Low-Pass Filter After the modulation, the signal is amplified before being filtered through a high-pass filter. This removes the noise caused by the DC current (amplifier 1/f noise). The signal is taken through demodulation and before filtering through the low-pass filter to give an amplified signal of direct current to the output display. Part 2: Design a 8-bit counter and a 4-to-7 decoder for the Seven-Segment display. The output voltage signal from the analogue circuit should then be converted into an 8-bit digital signal, which represents the levels of the motor speed. You can choose the generic 8-bit ADC device from the Proteus library => Modelling Primitives => ADC_8 for this task. Following is an example connection of the ADC convertor that you can refer to when you design your circuit. Design a 8-bit synchronous counter by using D-type flip-flops. The counter should be driven by a CLK signal running at 256k Hz. You should show how the counter is designed, and simulate the circuit. Marks allocation: [20%] The design of the 8-bit synchronous counter was done using D-type flip-flops and a clock as demonstrated in figure 8 below. The simulation of the counter was accomplished using regular ripple counter and additional NAND gating. It forced a reset of the input digital signal to 0 after the 5 states. At this point, the counter begins to count 0, 1, 2, 3, 4, 5, 6 and 7 and repeats the process. Instead of moving from 7 to 8, the ripple counter is compelled to move from state 7 to 0. Figure 8: 8-Bit Synchronous Counter Using the input signals, the ripple counter was reset to 0 as required. In this project, it is reset to 0 as the counter tries to switch from state 7 to state 8. A divide-by-8 counter is presented in figure 8 above. As it is evident, the NAND gate senses state 8 as Qc and Qa both have a value 1. At this point, the NAND gate goes on and then resets the counter to a zero state. This action gives a complicated timing sequence of wave forms as shown in figure 9 below. When the clock falls to zero after 40ns, Qa turns to a 1, making the counter go to state 8. At this point, the two inputs to the NAND gate are at state 1. At the point of 50ns, (which is the switch delay time of the NAND gate), the NAND output goes to 0. This resets the flip-flops. The clearing operation takes 40 ns at maximum. The output of this flip flop is finally reset to 90 ns (the total of the intervals covered 40, 10 and 40ns) at the end of the clock falling edge. 8.3.2 Producing the Symmetric Waveform The subsequent square waves are produced through the divide – by - 8 counters, which were initially described as asymmetric (Null & Lobur, 2006). It is zero for 7 input cycles and one for 1 input - clock cycle, which displays the input clock as well as the divide – by – 8. Figure 9: Symmetric Waveform The MSB output of the counter should be used to connect to the clock terminal of ADC_8 converter. The value of the output of the adc_8 converter should be displayed in two 7-segment display units, the MSB four bits are displayed in one and the LSB four bits in another. In order to achieve this, you should design the 4-to-7 decoder for the 7-segment display, as detailed below. A 7-segment display decoder is commonly used to display a particular number representation using a display composed of seven LED segments. The diagram below represents a 7-segment display decoder which converts a 4-bit binary number into a collection of symbols to be displayed: Your 7-segment decoder should accept a 4-bit binary numbers [x3, x2, x1, x0], which represents integer numbers 0 - 9 and letter A, B, D d, E, F. The decoder should output signals “0” to drive the appropriate segments (a-g) of a standard 7-segment display as shown above. The symbols used should be: Complete the truth table for the 4-to-7 decoder: Use Karnaugh map to simply the logic expressions for the 4-to-7 decoder. You should convert the expressions from SOP form to POS form so that you can make use of the NAND gates only. Simulate your decoder circuit and demonstrate that the circuit is working properly. [20%] Figure 10: Simulation of 4 –to - 7 Decoders The Design in figure 10 is a demonstration of a 4 to 7 decoder for converting a 4-bit numerical input into a Hexadecimal numerical display as presented in Figure 11 below. Table 1 below is a complete truth table that the gives the 7-segment digital output with the application of negative logic. From the table, the project determines the equations for the 7 segment displays and reducing their values using a Karnaugh-map. The result of the working 7 segment digital signal is shown below. Fig. 11: 7 Segment Digital Displays The decoder symbol is inserted into the schematic design to connect the 8 -bit asynchronous counter outputs appropriately. We repeat the process to simulate the whole design for the verification of the outputs using the Table below. hex C0 C1 C2 C3 HEX0[0] HEX0[1] HEX0[2] HEX0[3] HEX0[4] HEX0[5] HEX0[6] 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Table 1: Truth for the 4-to-7 Decoder Connect the 8-bit counter outputs to two 4-7 decoders which drive two seven-segment display units, respectively. Simulate the circuit and demonstrate that entire circuit works properly. [10%] Figure12: Connecting 8 Bit Counter to 7 – Segment Display The 8 bit counter was connected to the 7 segment display as shown in figure 12 below. It gives an output in form of an alpha-numeric display. The seven segment display was an array of 7 LEDs for the display of the hexadecimal numerical values between 0000 and 1111 through the illumination of the LED combinations. In many instances, all the LED’s in the 7 - segment display had a shared cathode. To illuminate the LED, one had to assert special logic level in the input. Figure 13: Output of the LED Combination with the 8 Bit Counter Each of the digit shared the eight control signals to produce light in each individual segment of the LEDs. For the lighting of any given segment, we drive the segment control to LOW together with the related anode signal for the individual character (Maini, 2007). For example, in order to display a value of 2, the segments a, b, c, d, e, f and g are set to 1101100 respectively. In the presence of the NAND logic gate, logic LOW turns on the individual LED segment while logic high turns the segment off. The anode control for the rest of the character segments remains HIGH. Seven Segment Unit In the application of the clock signal, we need to produce a system, which does time multiplexing between signal AN3 and AN0 as shown in figure 14 below. This needs the usage of certain sequential logic components. In figure 15 below, the results of the output signals appear as a block, providing the required as per the description below. Figure 14: Block Results of the 8 Bit Counter and 7 segment Display Figure 16: The Anode Driver Clk refers to the Clock for the component, which can move to 1 Hz Reset refers to this block being made to logic 1 CE enables the component on logic 1 O1 and O0 refers to the binary form of the active output AN0–AN3 refers to the low outputs for activating the chosen anode. In every clock period, ther is only one active output between AN3 and AN0, while O1O0 matches the activated signal 00, 11, 10 or 01. The O1O0 sequence is thus generated through an 8 bit counter. The output of an 8 - bit counter runs cycles between 0000000 and 1111111 in an increasing of the count every time the clock moves up one step. References Null, L & Lobur, J (2006). The essentials of computer organization and architecture. Jones & Bartlett Publishers. p. 121. Maini. A.K. (2007). Digital Electronics Principals, Devices and Applications. Chichester, England.: Jonh Wiley & Sons Ltd. Brown, S. & Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL Design. 3rd ed. New York, N.Y.: Mc Graw Hill. Kleitz , W. (2002). Digital and Microprocessor Fundamentals: Theory and Application. 4th ed. Upper Saddler Reviver, NJ: Pearson/Prentice Hall. Chan Y. K. and Lim, S. Y. (2008). Progress In Electromagnetics Research B, Vol. 1, 269–290, 2008,"Synthetic Aperture Radar (SAR) Signal Generation, Faculty of Engineering & Technology, Multimedia University, Jalan Ayer Keroh Lama, Bukit Beruang, Melaka 75450, Malaysia. Read More