Boost Converter Design - Coursework Example

ELEC9711 – Advanced Power Electronics Student Name Instructor College Course Name Executive Summary 100W converter has been designed and simulated using LTSpice and powersim. It is designed to have 3 different switching frequencies of 20 KHz, 50 KHz and 100 KHz. The designed circuit is made up of of two inductors, two capacitors, a switch and a diode. Combinations of capacitors and inductors are also used as filters. It was simulated but varying input voltage and keeping oscillation at 50 kHz. The induced emf in the primary winding due to its leakage flux which considered as a voltage drop in the winding leakage reactance. Similarly the voltage drops in secondary winding due to leakage flux. Table of Contents Executive Summary 2 Introduction 4 Background Theory 4 Stage 1- Circuit Design and Operation 5 The CCM and DCM Boundary Operation 6 Stages 2: Simulation Results for 50 kHz design 8 40Vin, 20W out 9 40Vin, 100W out 10 60Vin, 20W out 11 60Vin, 100W out 12 Stages 3: Magnetic component design 13 Peak value of the current 15 Conclusions 18 References 19 Introduction The main purpose of this design project is to design a 100W converter using the switching power supply topology of Ćuk converter. The input and output of this design need to meet particular requirements, which input voltage can vary between 40V and 60V, with nominal input of 50V. Meanwhile, the output load could vary from 20W to 100W, the voltage output ripple, however, should not excess 1% under any worst cases conditions. Background Theory The Ćuk converter is a type of DC-DC converter that has an output voltage magnitude that is either greater than or less than the input voltage magnitude. The non-isolated Ćuk converter could only have opposite polarity between input and output. It uses a capacitor as its main energy-storage component, unlike most other types of converters that use an inductor. A typical Ćuk converter is non-isolated type, which consists of two inductors, two capacitors, a switch and a diode. Its schematic can be seen in figure 1. Figure 1 the schematic of a non-isolated Ćuk converter It is an inverting converter, so the output voltage is negative with respect to the input voltage. The capacitor C1 is used to transfer energy and is connected alternately to the input and to the output of the converter through the commutation of the transistor and the diode in on stage and off stage. Figure 2 The On Stage (Left) and the Off Stage (Right) of the Ćuk converter The two inductors L1 and L2 are used to convert respectively the input voltage source, Vd, and the output voltage source, C, into current sources. Within a short time an inductor can be considered as a current source as it maintains a constant current. This conversion is necessary because if the capacitor were connected directly to the voltage source, the current would be limited only by load resistance and resulting in a high energy loss. Charging a capacitor with an inductor prevents resistive current limiting and its associated energy loss. This report will mainly describe the device working in different given specification conditions and requirements in its continuous boundary operations. Stage 1- Circuit Design and Operation First of all, it is assumed that all components involved in the circuit are ideal and the inductor current maintains continuous and the output voltage of Vo is constant by the large capacitor C1 and C during the communication durations. Under the combination functioning of the capacitors and the volt-sec balances in current source inductors L1 and L2, the equation hence held for Ćuk converter: And from power balance: Thus, for Vd = 40V; D1 = 5/7; for Vd = 60V; D2 = 5/8; Note that, the negative sign has been eliminated by oppositely measuring the voltage due to the feature of Ćuk converter. Therefore, the range of duty cycle, D, is varying between 5/7 and 5/8, for later easier calculation the duty cycle has not been digitised and remain in fractions. The duty cycle here determines the output to input voltage ratio. While the duty cycle changes it could affect the sign of the output voltage when it change from 0 to 1 and the utilisation of the output need to be considered from less than the input voltage to larger than it. The CCM and DCM Boundary Operation This design project requires the device to work under boundary condition when at steady state. Thus, the ΔiL1 = 2Id, and ΔiL2 = 2Io at boundary condition. While from output side we got Io = Vo/ R, and the ratio of Io/Id we got: From the equations listed on the previous page, we could firstly find Io for each condition: Output power = 20W: Vo = 100V => Io = 0.2A For Vd = 40V; D1 = 5/7 => Id = 0.50A For Vd = 60V; D2 = 5/8 => Id = 0.33A Hence: for Vd = 40V; ΔiL1 = 1A For Vd = 60V; ΔiL1 = 0.66A ΔiL2 = 0.4A; And so forth, according to the equations of ΔiL1 and ΔiL2, the L1 and L2 could be deduced for each frequency required. In addition, for continuous condition, iL1,min >= 0, So: From the equation above, it could be deduced that: So for L2min is similar that: Therefore, under different circumstances, the Inductances for L1 and L2 could be deduced and listed below in the table. Vd/V Fs/Hz L1/H L2/H 40 20000 1.43E-03 3.57E-03 60 20000 2.81E-03 4.69E-03 40 50000 5.71E-04 1.43E-03 60 50000 1.13E-03 1.88E-03 40 100000 2.86E-04 7.14E-04 60 100000 5.63E-04 9.38E-04 40 20000 2.86E-04 7.14E-04 60 20000 5.63E-04 9.38E-04 40 50000 1.14E-04 2.86E-04 60 50000 2.25E-04 3.75E-04 40 100000 5.71E-05 1.43E-04 60 100000 1.13E-04 1.88E-04 Table 1 the minimum inductance should be applied under different circumstances for L1 and L2 The deduction of output capacitor is the similar as the one in the buck converter which could be expressed as below: The required capacitance of C1 and Co are listed below which computed by MS Excel as did for inductances. Because of the ripple is required less than 1%, so the worst case here is the ratio of ΔVo/Vo = 1% = 0.01. Vd/V P/W Fs/Hz C1 C 40 20 20000 6.25E-06 2.50E-06 60 20 20000 4.17E-06 2.50E-06 40 20 50000 2.50E-06 1.00E-06 60 20 50000 1.67E-06 1.00E-06 40 20 100000 1.25E-06 5.00E-07 60 20 100000 8.33E-07 5.00E-07 40 100 20000 3.13E-05 1.25E-05 60 100 20000 2.08E-05 1.25E-05 40 100 50000 1.25E-05 5.00E-06 60 100 50000 8.33E-06 5.00E-06 40 100 100000 6.25E-06 2.50E-06 60 100 100000 4.17E-06 2.50E-06 Table 2 the capacitance that was required for CCM in C1 and Co Stages 2: Simulation Results for 50 kHz design The Cuk converter is divided into three sections that is output, input and middle section. During simulation a 50 kHz switching frequency was used because of the low switching loss and component count. It has a high power density with high efficiency. The circuit was simulated using LTSspice IV and its result presented below. 40Vin, 20W out 40Vin, 20Wout. From the above simulation diagrams it can be noted that the waveform is stable as compared to other wave forms for the selected frequency. The waveforms for other form of conditions are almost similar but they have differences as shown. For 40V, 100W out, the waveform shows a wider range. We can also note that the wave form. 40Vin, 100W out 60Vin, 20W out 60Vin, 100W out The current, voltage and power waveforms for 50 kHz and with a duty ratio of 1% are shown below. This indicates that there is a high voltage pulse. It show the measures losses together with the model curves. The obtained good matching validates the presented model The wave forms as noted above for the frequency does not show great distortion for 40Vin, 20Wout. The last one shows a steady output power with time for frequencies. The value of distortion did not exceed 1%. Stages 3: Magnetic component design In designing magnetic component Ferrite cores have been used with a large resistivity r and does a not experience ohmic loss. It has Bs = 0.3 T (T = tesla = 104 oe) it has the largest performance factor at 100 kHz. It should be double-E core because of easiness to fabricate winding. It is shown below Will connected as Peak value of the current f= = 20 kHz T = = 0.05 , T = = 0.02 , fc = = 0.4 f= = 50 kHz T = = 0.02 , T = = 0.01 , fc = = 0.5 This is in small percentage of total flux because it flows mainly through non-magnetic paths. The flux which links only with primary winding is known as Primary leakage flux (). The flux which links with both primary as well as secondary is common flux (), and the flux which links with secondary only is known as secondary leakage flux (). The leakage flux associated with the winding is proportional to the current passing through it. In this case , since the windings carry alternating current, the leakage also periodically vary with time. The winding is placed in its own leakage flux which is time varying, and hence, there is an induced emf. The induced emf in the primary winding due to its leakage flux is ( N1.) which is (L1.) and can be considered as a voltage drop in the winding leakage reactance. Similarly the voltage drop in secondary winding due to leakage flux is (N2. which is (L12.). Here L11 and L12 are the leakage inductances of the two windings. With sinusoidal ex citation, the r.m.s leakage reactance drop in primary = I2..L1 2 = I2. X2 , where is the supply frequency in radians/sec. and x1 and x2 are the leakage reactance of the two windings. Gap length = ( ) = 0.108mm We select 0.075mm Power dissipation Current density = (2.5 A)/(0.2 mm2) = 5 A/mm2 Ro = = = 40.4oC/W P= /R =50/ 30 = 1.67W Pw = 1.67/(1+5) = 0.2778W • Flux density and core loss • Vpri,max = Npri Ac Bac = (1.414)(40) = 56.56 V • Bac =56.56(32)(0.952x10-4 m2)(2)(50KHz) = 0.1357 T • Pcore = (6.15 cm3)(1.5x10-6)(100 kHz)1.3(135.7 mT)2.5 = 1.67 W Turns = = 41 turns Wire size = K1 A multi-strand wire with at least 30 strands of 0.1 mm diameter wire meets this specification, with a dc resistance of 7.25×10-4Ω/cm @20ºC Conclusions To conclude, Cuk converter is used in DC/DC conversion the Cuk converter is a buck – boost converter with the inductor split to form a transformer, so that the voltage ratios are multiplied with an additional advantage of isolation. The Cuk converter is a type of  DC/DC converter that has an output voltage magnitude that is either greater than or less than the input voltage magnitude. The output signal can be smoothed out by a capacitor the current flows through the diode; when the source voltage starts to drop and then changes polarity, the capacitor discharges through the resistor. The capacitor cannot discharge through the diode because that would send current the wrong way through the diode. The discharge keeps the voltage VR up. By making the RC time constant (t=RC) long enough, the discharge through the resistor can be made to continue until the source voltage turns positive again. Circuit involving more than one diode can be arranged to make a full-wave rectifier. The Cuk converter is another converter topology to provide a regulated output voltage from an input voltage that varies above and below the output voltage. The drawbacks are the requirements for a higher input-voltage ripple, a much larger capacitor. References Falin, J., 2010. Designing DC/DC converters based onZETA topology. Analog Applications Journal Glover, J.D., Sarma, M.S, & Overbye, T.J., 2007. Power System Analysis and Design. Osprey : Nelson Engineering Hurley,W.G & Zhang, J. 2013. Design and Implementation of Magnetic Components for LLC Resonant Converters. Electrical and Electronic Engineering National University of Ireland, Galway Hurley,W.G & Wölfle, W. 2012. High Frequency Magnetic Circuit Design for Power Conversion. Electrical and Electronic Engineering National University of Ireland, Galway Irving, B. & Jovanović, M.M., 2002. Analysis and Design of Self-Oscillating Flyback Converter. Delta Products Corporation, Power Electronics Laboratory. Read More

Under the combination functioning of the capacitors and the volt-sec balances in current source inductors L1 and L2, the equation hence held for Ćuk converter: And from power balance: Thus, for Vd = 40V; D1 = 5/7; for Vd = 60V; D2 = 5/8; Note that, the negative sign has been eliminated by oppositely measuring the voltage due to the feature of Ćuk converter. Therefore, the range of duty cycle, D, is varying between 5/7 and 5/8, for later easier calculation the duty cycle has not been digitised and remain in fractions.

The duty cycle here determines the output to input voltage ratio. While the duty cycle changes it could affect the sign of the output voltage when it change from 0 to 1 and the utilisation of the output need to be considered from less than the input voltage to larger than it. The CCM and DCM Boundary Operation This design project requires the device to work under boundary condition when at steady state. Thus, the ΔiL1 = 2Id, and ΔiL2 = 2Io at boundary condition. While from output side we got Io = Vo/ R, and the ratio of Io/Id we got: From the equations listed on the previous page, we could firstly find Io for each condition: Output power = 20W: Vo = 100V => Io = 0.

2A For Vd = 40V; D1 = 5/7 => Id = 0.50A For Vd = 60V; D2 = 5/8 => Id = 0.33A Hence: for Vd = 40V; ΔiL1 = 1A For Vd = 60V; ΔiL1 = 0.66A ΔiL2 = 0.4A; And so forth, according to the equations of ΔiL1 and ΔiL2, the L1 and L2 could be deduced for each frequency required. In addition, for continuous condition, iL1,min >= 0, So: From the equation above, it could be deduced that: So for L2min is similar that: Therefore, under different circumstances, the Inductances for L1 and L2 could be deduced and listed below in the table.

Vd/V Fs/Hz L1/H L2/H 40 20000 1.43E-03 3.57E-03 60 20000 2.81E-03 4.69E-03 40 50000 5.71E-04 1.43E-03 60 50000 1.13E-03 1.88E-03 40 100000 2.86E-04 7.14E-04 60 100000 5.63E-04 9.38E-04 40 20000 2.86E-04 7.14E-04 60 20000 5.63E-04 9.38E-04 40 50000 1.14E-04 2.86E-04 60 50000 2.25E-04 3.75E-04 40 100000 5.71E-05 1.43E-04 60 100000 1.13E-04 1.88E-04 Table 1 the minimum inductance should be applied under different circumstances for L1 and L2 The deduction of output capacitor is the similar as the one in the buck converter which could be expressed as below: The required capacitance of C1 and Co are listed below which computed by MS Excel as did for inductances.

Because of the ripple is required less than 1%, so the worst case here is the ratio of ΔVo/Vo = 1% = 0.01. Vd/V P/W Fs/Hz C1 C 40 20 20000 6.25E-06 2.50E-06 60 20 20000 4.17E-06 2.50E-06 40 20 50000 2.50E-06 1.00E-06 60 20 50000 1.67E-06 1.00E-06 40 20 100000 1.25E-06 5.00E-07 60 20 100000 8.33E-07 5.00E-07 40 100 20000 3.13E-05 1.25E-05 60 100 20000 2.08E-05 1.25E-05 40 100 50000 1.25E-05 5.00E-06 60 100 50000 8.33E-06 5.00E-06 40 100 100000 6.25E-06 2.50E-06 60 100 100000 4.17E-06 2.50E-06 Table 2 the capacitance that was required for CCM in C1 and Co Stages 2: Simulation Results for 50 kHz design The Cuk converter is divided into three sections that is output, input and middle section.

During simulation a 50 kHz switching frequency was used because of the low switching loss and component count. It has a high power density with high efficiency. The circuit was simulated using LTSspice IV and its result presented below. 40Vin, 20W out 40Vin, 20Wout. From the above simulation diagrams it can be noted that the waveform is stable as compared to other wave forms for the selected frequency. The waveforms for other form of conditions are almost similar but they have differences as shown.

For 40V, 100W out, the waveform shows a wider range. We can also note that the wave form. 40Vin, 100W out 60Vin, 20W out 60Vin, 100W out The current, voltage and power waveforms for 50 kHz and with a duty ratio of 1% are shown below. This indicates that there is a high voltage pulse. It show the measures losses together with the model curves. The obtained good matching validates the presented model The wave forms as noted above for the frequency does not show great distortion for 40Vin, 20Wout.

Read More