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Combinational Logic Circuits - Lab Report Example

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The report "Combinational Logic Circuits" focuses on the critical, and thorough analysis of the major issues in combinational logic circuits. The main aim of this practical is to make us familiar with the performance analysis of combinational logic circuits…
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Combinational Logic Circuits
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Extract of sample "Combinational Logic Circuits"

The main aim of this practical is to make us familiar with the performance analysis of combinational logic circuits. It is imperative to note that this practical should be done by simulating the sum-of-products (SOP) and product-of-sum (POS). Also, there would be the usage and comparison of NAND and BOR gates in this lab.

The goal of this experiment was to determine how to design a circuit that must use the properties of AND, NAND, and BOR and as a result, prove how both NAND and BOR can give the same outcome as well as operate give the same results through the values of inputs and output. In addition to that, the same outputs must conclude in each of the NAND and BOR circuits. The properties were tested at the time of functional simulation, and proven during the hardware testing when the light on the FPGA board was programmed to turn on given there was an output of 1. The timing delay was also tested through the timing simulation. 

The outcome of the waveform was that it worked successfully the way it was supposed to. The design of the three circuits was made as an RTL schematic and each of the circuits had specific settings. The second step was to transfer the three circuit designs through USB to the FPGA for them to be tested as to whether they worked properly or not.

The function variables are represented in a timely interval and there are variations with time. As a result, the representation information that is accrued from the circuit can be obtained accordingly within the graph. Following the same logic as per the functional simulation, the bumps in the graph represent the function when it equates to 1, while the straight lines represent the function when it equates to 0. Of importance to note is that the graph also reveals the propagation delay that occurs each time variables go through the logic gates in the timing simulation.

By thoroughly following the steps in the lab manual provided, the three circuits were successful in reaching the main goal of the lab. The objective was to prove the assumption that the BOR gate gives the same output as the NAND gate. This proved TRUE. Also, the results concluded that the output of the two circuits was the same given the same inputs.

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